CEO Interview with Dave Kelf, CEO of Breker Verification Systems

Key Takeaways

• Breker posted 35% revenue growth in 2025, matching prior year
• Added Bangladesh engineering facility to expand support capacity
• RISC‑V SystemVIP now used in over half of global core projects
• Launched AI‑driven SoC verification flow with Moores Lab AI
• Targeting test‑content generation market for large‑device system verification

Pulse Analysis

The semiconductor verification landscape is undergoing a paradigm shift as chip designs become more heterogeneous and AI‑centric. Traditional manual test‑bench creation can no longer keep pace with the explosion of cores, accelerators, and custom instructions. Breker’s synthesis‑based approach, which embeds AI planning algorithms, automates the generation of high‑coverage test scenarios, reducing engineer effort and shortening time‑to‑market. By partnering with Moores Lab AI, Breker introduced an end‑to‑end AI‑driven SoC verification flow that translates high‑level specifications into both C and SystemVerilog tests, a capability that resonates with companies seeking to validate complex multicore and GPU‑enabled designs.

RISC‑V’s open‑source architecture has surged in adoption, now powering more than half of new processor core projects worldwide. Breker’s enhanced SystemVIP suite and its leadership role in the RISC‑V International Certification program give it a strategic foothold in this expanding ecosystem. The addition of top‑10 semiconductor firms and two Magnificent 7 companies to its customer roster not only doubles its client base but also validates the company’s relevance to the most demanding design teams. This momentum is amplified by the new Arm Neoverse CSS SoCReady offering, which bridges the gap between ARM’s high‑performance cores and Breker’s verification expertise.

Looking ahead to 2026, the unserved market for system‑level test‑content generation presents a lucrative opportunity. As verification engineers grapple with increasingly complex SoC scenarios, Breker’s AI‑enhanced synthesis can uncover obscure corner cases that manual methods miss, delivering higher confidence in silicon before silicon tape‑out. This focus on automated test content aligns with broader industry trends toward AI‑augmented EDA tools, positioning Breker to capture a larger share of verification spend and to drive the next wave of productivity gains across the semiconductor supply chain.