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Different Types of Registers in Processor Architecture Explained ||RISC - V Processor Design || ABV

The video walks viewers through the core registers that underpin a RISC‑V processor, framing the discussion as part of a broader VLSI design series. It outlines each register’s purpose—addressing, data movement, instruction sequencing, and I/O handling—while tying them to the underlying bus architecture. Key insights include the interplay between the Memory Address Register (MAR) and Memory Data Register (MDR): MAR places the target address on the address bus, and MDR carries the actual data on the data bus. The Program Counter (PC) automatically increments to fetch the next instruction, while the accumulator serves as the primary scratch pad for ALU results. Additional registers such as the Instruction Register, Interrupt Register, and Output Register orchestrate control flow and external communication. The presenter illustrates concepts with concrete examples, loading address 002 into MAR to read data, and showing PC value 004 driving the next fetch. He also quantifies addressable memory: 16‑bit MAR yields 64 KB, 20‑bit yields 1 MB, and 32‑bit reaches 4 GB, underscoring the scalability of register width. Understanding these registers is vital for architects designing efficient RISC‑V cores, as they dictate how instructions are fetched, executed, and how data moves between CPU and memory. Mastery of this register set enables more effective debugging, performance tuning, and custom processor extensions.