A high‑density, hybrid AI chip could break Nvidia’s monopoly on LLM acceleration, unlocking faster model training and inference while reducing reliance on constrained silicon supplies.
The video announces a $500 million Series B round for a Google‑alumni startup aiming to challenge Nvidia’s dominance in large‑language‑model (LLM) hardware. Backed by quantitative‑trading firm Jane Street and AI‑focused investor Leopold Ashenbrenner, the company says the capital will fund a hybrid chip that fuses high‑bandwidth memory (HBM) with SRAM to achieve unprecedented computational density.
Founders argue that LLM compute demand is “insatiable” and that existing solutions either sacrifice throughput (HBM‑only) or latency (SRAM‑only). Their breakthrough lies in delivering the highest FLOPS per square‑millimeter while preserving low‑latency characteristics, a metric they claim surpasses Nvidia, Google TPU, Cerebras and Grok. The design will break backward compatibility to focus on large‑matrix, low‑precision operations, allowing the chip to split massive systolic arrays into smaller blocks for flexibility.
The team highlighted partnerships across the semiconductor supply chain: TSMC for logic wafers, SK Hynix, Samsung and Micron for memory, and a network of rack‑assembly providers. Final silicon is expected by year‑end, with volume manufacturing targeted for 2027. By eschewing legacy support, the startup hopes to deliver a “blank‑slate” architecture optimized for next‑generation LLM workloads.
If successful, the chip could reshape the AI hardware landscape, offering a domestically viable alternative to Nvidia’s GPUs and potentially easing the silicon shortage that threatens AI model scaling. Investors and cloud providers would gain a high‑throughput, low‑latency option, accelerating the rollout of ever‑larger language models and diversifying the supply chain.
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