AMD Medusa Point Leaked: 10 Cores, 32 MB L3 Cache, and First Geekbench Results for a Zen 6 APU

Key Takeaways

• 10‑core, 20‑thread APU with 32 MB L3 cache confirmed
• Base clock 2.4 GHz, boost around 2.0 GHz in sample
• Cache size 8 MB larger than current Ryzen AI 9 365
• Likely 28‑W and 45‑W TDP variants on FP10 platform

Pulse Analysis

The emergence of a Medusa Point engineering sample marks the first concrete glimpse of AMD’s upcoming Zen 6 mobile APU family. By expanding L3 cache to 32 MB—an eight‑megabyte jump over the Ryzen AI 9 365—AMD appears to be targeting workloads that benefit from larger on‑die memory, such as AI inference and high‑resolution content creation. The cache increase, coupled with a hybrid core architecture hinted by "4C4D" configurations, suggests a strategic shift toward balancing raw compute with efficiency in ultra‑portable devices.

Performance figures, while modest in clock speed, provide valuable context. The sample’s base frequency of 2.40 GHz and observed boost near 2.01 GHz reflect early‑sample power constraints rather than final silicon limits. Nevertheless, the multi‑core Geekbench score of 7,323 points indicates a scalable architecture that could rival current Intel Evo offerings once tuned for higher TDP envelopes. The reference to the "Plum‑MDS1" platform aligns with AMD’s FP10 roadmap, implying two power‑targeted SKUs—approximately 28 watts for thin‑and‑light notebooks and 45 watts for performance‑oriented ultrabooks.

For the market, Medusa Point’s specifications could redefine AMD’s positioning against Intel’s 13th‑gen mobile processors and Apple’s M‑series chips. A larger cache and hybrid core mix promise better multitasking and AI‑centric performance without sacrificing battery life, a key selling point for premium laptops. Analysts will watch for official announcements later this year, focusing on real‑world benchmarks, power‑efficiency claims, and pricing strategy, which will determine whether AMD can capture a larger share of the high‑end mobile segment.