AMD Zen 6 “Medusa Point” Appears on Geekbench – 10 Cores, 32 MB L3 Cache, and the First Credible Hint of FP10 Mobile

Key Takeaways

• Geekbench shows 10‑core, 32 MB L3 Zen 6 mobile sample.
• Cache increase suggests new architecture beyond current Zen 5 FP8.
• FP10 BGA platform linked to “Medusa Point” leak.
• Early sample clocks low; performance still speculative.
• Could signal AMD’s shift to larger cache in notebooks.

Pulse Analysis

The newly surfaced Geekbench record for "AMD Plum‑MDS1" provides the first tangible glimpse of AMD's upcoming Zen 6 mobile silicon, codenamed Medusa Point. Beyond the headline‑grabbing 10‑core, 20‑thread count, the most striking specification is the 32 MB L3 cache—significantly larger than the 24 MB found in the current Zen 5‑based FP8 Ryzen AI 300 series. This cache expansion hints at a redesign of the core complex, likely leveraging the FP10 BGA package that industry trackers have associated with Medusa Point. While the sample’s low clock speeds (2.40 GHz base, just over 2 GHz boost) reflect early‑sample power constraints, the architectural shift is evident.

AMD’s roadmap has long hinted at a transition from the FP8 platform to a newer FP10 socket for its next‑gen mobile processors. The FP10 package promises a different pinout and power delivery scheme, enabling higher core counts, larger caches, and potentially hybrid configurations that blend high‑performance Zen 6 cores with efficiency‑focused Zen 6c cores. If the 32 MB L3 cache is confirmed in production silicon, it could translate into noticeable gains in multi‑threaded workloads and cache‑sensitive applications such as AI inference and content creation—areas where AMD has been gaining ground. Moreover, the move may allow thinner thermal designs, giving OEMs more flexibility in chassis engineering.

For the broader market, Medusa Point could reshape the competitive dynamics of the notebook segment. Intel’s upcoming Meteor Lake and later Arrow Lake families aim to improve efficiency and integrate advanced graphics, but they still rely on relatively modest cache sizes. AMD’s larger cache and new package could offer a compelling performance‑per‑watt proposition, prompting OEMs to reconsider their CPU sourcing strategies for premium ultrabooks. However, the sample remains an engineering prototype; real‑world performance will depend on power management, silicon yield, and software optimization. Stakeholders should watch for official announcements later this year, which will clarify whether AMD can translate this early leak into a market‑ready advantage.