Are CCD Memories Coming Back?

Key Takeaways

• imec explores 3D “Punch & Plug” CCDs as DRAM alternative
• Vertical CCD cells could shrink below DRAM size, reducing cost
• IGZO channel replaces amorphous silicon for charge storage in CCD
• 2024 planar prototype showed strong performance, paving way for 3D parts
• SAM architecture aligns with modern cache designs, easing integration

Pulse Analysis

The memory landscape is at a crossroads as DRAM struggles to scale below its current node. Traditional DRAM cells rely on a transistor‑capacitor pair, and the capacitor’s physical limits are becoming a roadblock. imec’s approach sidesteps this bottleneck by leveraging the proven "Punch & Plug" technique from 3D NAND, stacking CCD transistors vertically. This architecture not only promises higher bit density but also reduces the transistor count per bit, translating into lower manufacturing costs.

A key innovation is the substitution of the standard amorphous‑silicon channel with indium‑gallium‑zinc‑oxide (IGZO). IGZO offers superior charge‑storage characteristics suited to the CCD’s serial‑access nature, while maintaining compatibility with existing 3D NAND process flows. The 2024 planar demonstration validated the material stack, showing fast charge transfer and low leakage—critical metrics for any memory competing with DRAM. With a 3D implementation on the horizon, imec aims to deliver a memory that can be produced at scale using existing NAND fabs.

Beyond raw density, CCDs fit naturally into modern processor architectures that rely heavily on cache hierarchies. Serial‑access memory (SAM) can feed data in bursts that align with cache line sizes, reducing latency penalties that plagued early CCD designs. This synergy, combined with the cost advantage, makes CCDs attractive for AI‑specific compute‑in‑memory solutions where massive bandwidth and energy efficiency are paramount. If imec’s roadmap succeeds, the industry could see a new class of memory chips that challenge DRAM’s dominance in servers, edge devices, and high‑performance computing.