IBM and Lam Research Announce Collaboration to Advance Sub-1nm Logic Scaling

Key Takeaways

• Five‑year IBM‑Lam deal targets sub‑1 nm logic scaling
• Joint work focuses on new materials and High‑NA EUV processes
• Collaboration leverages IBM research and Lam’s equipment platforms
• Goal: high‑yield, low‑power transistors for AI era

Summary

IBM and Lam Research have signed a five‑year partnership to push logic scaling below the 1 nm node. The collaboration will co‑develop novel materials, advanced etch and deposition processes, and High‑NA EUV lithography techniques to enable sub‑1 nm transistors. Leveraging IBM’s Albany NanoTech research and Lam’s Aether dry resist, Kiyo etch, and ALTUS Halo deposition platforms, the teams aim to validate full process flows for nanosheet and nanostack devices. The effort builds on a decade‑long relationship that delivered 7 nm, nanosheet, and the world’s first 2 nm chip.

Pulse Analysis

The semiconductor industry faces an imminent scaling wall as traditional planar devices approach physical limits. Sub‑1 nm logic nodes demand breakthroughs in materials science, etch chemistry, and lithography resolution. High‑NA EUV, with its shorter wavelength and higher numerical aperture, offers the necessary pattern fidelity, but requires compatible dry resist formulations and precise process integration to avoid yield loss. By tackling these challenges head‑on, IBM and Lam aim to keep performance gains on track for data‑center and edge AI applications.

IBM’s Albany NanoTech Complex brings deep research expertise in nanoscale device physics, while Lam supplies end‑to‑end manufacturing tools such as the Aether dry resist, Kiyo and Akara etch platforms, and ALTUS Halo deposition systems. The five‑year agreement formalizes joint development of nanosheet and nanostack architectures, as well as backside power delivery schemes, enabling a seamless transition from laboratory prototypes to production‑ready flows. This partnership builds on a proven track record that delivered the first 2 nm chip in 2021, demonstrating both companies’ ability to translate cutting‑edge research into commercial silicon.

Success in sub‑1 nm scaling will have ripple effects across the tech ecosystem. Lower power consumption and higher transistor density directly benefit AI accelerators, cloud infrastructure, and emerging workloads like generative models. Moreover, establishing a reliable High‑NA EUV process lowers barriers for other fabless designers, potentially reshaping the competitive landscape away from legacy nodes. As the collaboration progresses, industry observers will watch for early silicon demonstrations that could set new performance benchmarks and influence future roadmaps for both established and emerging semiconductor players.