NEO Semiconductor Demonstrates 3D X-DRAM Proof-of-Concept, Secures Strategic Investment to Advance AI Memory

Key Takeaways

• 3D X‑DRAM POC achieves <10 ns read/write latency.
• Data retention exceeds 1 s at 85 °C, 15× JEDEC standard.
• Endurance surpasses 10¹⁴ cycles, indicating high reliability.
• Process uses existing 3D NAND infrastructure, reducing fab cost.
• Strategic investment led by Stan Shih backs next‑phase development.

Pulse Analysis

The AI boom is stretching conventional DRAM to its physical limits, prompting the industry to explore three‑dimensional memory structures that can pack more bits per wafer. 3D X‑DRAM, NEO Semiconductor’s answer, builds on the proven 3D NAND stack, which already exceeds 300 layers in high‑volume production. By adapting the same equipment and materials, NEO sidesteps the massive capital outlay typically required for new memory nodes, offering a faster, lower‑cost path to the terabit‑scale capacities demanded by next‑gen models.

NEO’s proof‑of‑concept chips deliver compelling metrics: read/write latency under 10 nanoseconds, data‑retention and disturbance times above one second at 85 °C—far surpassing the 64 ms JEDEC benchmark—and endurance beyond 10¹⁴ cycles. These figures demonstrate that 3D X‑DRAM can meet, and even exceed, the speed and reliability expectations of traditional DRAM while adding the density benefits of vertical stacking. The use of mature 3D NAND processes also means lower power consumption per bit, a critical factor for data‑center efficiency and edge AI deployments.

The strategic investment from a consortium led by Stan Shih adds financial muscle and credibility, positioning NEO to accelerate array‑level development and forge licensing or co‑development deals with established memory players. As the industry pivots toward 3D architectures, NEO’s approach could become a cornerstone of future AI system designs, offering a scalable, cost‑effective alternative to conventional DRAM. The upcoming presentation at the Future of Memory and Storage conference will likely attract further partnership interest, potentially reshaping the competitive landscape of high‑performance memory.