Silicon Storage Technology Assigned Four Patents

Key Takeaways

• Four new U.S. patents granted to Silicon Storage Technology
• Adaptive bias decoder improves voltage control for NVM arrays
• Coarse‑fine programming method speeds write while maintaining precision
• Integrated planar split‑gate and FinFET process unifies memory and logic
• Output block adds on‑chip ADC for faster readout

Pulse Analysis

Silicon Storage Technology’s latest patent suite underscores the accelerating pace of innovation in non‑volatile memory (NVM). The adaptive bias decoder patent tackles a long‑standing challenge: delivering precise source‑line voltages across large memory arrays while minimizing power draw. By dynamically adjusting bias based on operating conditions, the decoder can reduce leakage and improve read/write reliability, a critical advantage for high‑density storage used in cloud servers and AI workloads.

Equally notable is the coarse‑and‑fine programming method, which separates the write operation into a rapid bulk phase followed by a precision tuning phase. This two‑step approach shortens overall write latency without sacrificing the tight current margins required for multi‑level cell (MLC) and triple‑level cell (TLC) architectures. Coupled with the new output block that integrates a current‑to‑voltage converter and on‑chip analog‑to‑digital conversion, SST can deliver faster, more accurate data retrieval, reducing the need for external conversion circuitry and lowering system‑level power consumption.

The planar split‑gate device formation patent bridges memory and logic by embedding split‑gate NVM cells alongside high‑voltage (HV) devices and FinFET logic on a single substrate. This monolithic integration promises higher transistor density and shorter interconnects, enabling more compact, energy‑efficient modules. As data centers seek to shrink footprints and improve performance per watt, SST’s expanded IP portfolio could translate into commercially viable products that challenge incumbents like Samsung and Micron, while also opening licensing opportunities for fabless designers targeting emerging edge‑computing applications.