📈⏳ The Broken Bargain of Moore’s Law

Key Takeaways

• TSMC delays High‑NA EUV adoption until 2029 over cost.
• Cost per transistor stopped falling in 2011, now rising again.
• High‑NA EUV promised cheaper chips but may break economic model.
• Slowing Moore’s Law could curb AI and cloud hardware growth.

Pulse Analysis

Moore’s Law has long been framed as both a physical observation and an economic contract: each new generation of transistors arrives at a lower cost per operation. Over five decades, semiconductor manufacturers turned steep learning curves into cheaper smartphones, affordable cloud infrastructure, and the explosive growth of AI workloads. That bargain relied on a relentless decline in cost per transistor, a trend that began to flatten around 2011, even as lithography advances like EUV temporarily rescued the curve.

ASML’s High‑NA EUV system, priced near $300 million per unit, promises sub‑10‑nanometer patterning that could once again shrink chips while reducing wafer‑dollar costs. TSMC’s decision to postpone its deployment until after 2029 signals that the price premium outweighs the anticipated efficiency gains, effectively breaking the cost‑down promise. The reversal of the transistors‑per‑wafer‑dollar metric suggests that future nodes may no longer be economically viable without radical cost reductions or new business models.

The broader impact reaches beyond chip fabs. Cloud providers and AI developers count on ever‑cheaper compute to sustain rapid model scaling; rising silicon costs could compress profit margins and slow innovation pipelines. Industry players may accelerate alternative approaches such as advanced packaging, heterogeneous integration, or even shift toward specialized accelerators that sidestep the most expensive lithography steps. Investors and policymakers will watch closely as the economics of Moore’s Law evolve, redefining the competitive landscape of the global semiconductor ecosystem.