Akeana Partners with Axiomise for Formal Verification of Its Super-Scalar RISC-V Cores

Why It Matters

Formal verification eliminates hidden bugs and inefficiencies, safeguarding multi‑billion‑dollar tape‑outs and accelerating time‑to‑market for high‑performance RISC‑V IP.

Key Takeaways

• Formal verification uncovered functional bugs and redundant logic.
• Optimization reduced potential silicon re‑spin costs.
• Formal methods ensured PPA targets for 4 nm design.
• Partnership showcases RISC‑V cores meeting enterprise reliability.
• Axiomise tools integrated with commercial EDA for full sign‑off.

Pulse Analysis

The semiconductor industry is confronting unprecedented design complexity as process nodes shrink to 4 nm and beyond. Super‑scalar, out‑of‑order RISC‑V cores like Akeana’s Alpine introduce intricate control paths, speculative execution, and numerous corner cases that traditional simulation struggles to cover. Formal verification, which mathematically proves that every reachable state satisfies defined properties, offers an exhaustive safety net, ensuring functional correctness and catching subtle bugs that could otherwise escape detection.

Akeana’s partnership with Axiomise demonstrates how formal methods translate into tangible design benefits. Within a few months, Axiomise’s formalISA®, footprint®, and floatrix® tools pinpointed both functional defects and redundant logic, allowing Akeana to streamline its RTL before tape‑out. This early optimization not only mitigates the financial and schedule risks of a silicon re‑spin but also improves power, performance, and area (PPA) metrics—critical factors for competitive 4 nm products targeting data‑center, automotive, and AI workloads.

Beyond the immediate project, the collaboration signals a broader shift in the RISC‑V ecosystem. As open‑source architectures gain traction across diverse markets, customers demand the same reliability guarantees traditionally reserved for proprietary IP. Formal verification provides that assurance, enabling manufacturers to deliver production‑ready cores with confidence. The success of Alpine’s formal sign‑off suggests that similar partnerships will become a standard part of the semiconductor development flow, accelerating innovation while preserving quality and cost efficiency.