Enabling Seamless Monitoring, Test, And Repair In Multi-Die Designs

Why It Matters

Reliable test and repair for multi‑die packages unlocks faster time‑to‑market and reduces risk in AI and safety‑critical systems, making advanced packaging commercially viable.

Key Takeaways

• Multi‑die designs accelerate AI hardware performance
• Hidden chiplets complicate traditional test flows
• IEEE 1838 provides slow‑speed inter‑die test access
• Synopsys UCIe MTR enables high‑speed monitoring and repair
• Demo proves full‑stack access and signal‑integrity validation

Pulse Analysis

Multi‑die architectures, leveraging 2.5D and 3D integration, have become essential as single‑die scaling stalls under AI’s relentless demand for bandwidth and power efficiency. By stacking chiplets, designers can mix process nodes, reuse proven IP, and shrink footprints, delivering higher throughput than conventional PCB interconnects. Yet the very advantage of dense stacking creates blind spots: many internal dies lack direct probe points, inflating test complexity and jeopardizing yield. Addressing these blind spots is now a strategic priority for fabs and OEMs alike.

To bridge the test gap, industry standards and specialized IP are converging. IEEE 1838 defines a universal test access architecture for slow‑speed inter‑die links, while Synopsys’s UCIe Monitoring, Test & Repair (MTR) IP extends visibility to high‑speed PHYs. Complementary SLM modules—EXTRAM, Signal Integrity Monitor, SMS, CDM, and HSAT—provide real‑time health metrics, built‑in self‑test for memories, and adaptive high‑bandwidth testing over functional interfaces such as PCIe. Together, these tools transform previously hidden pathways into observable, reconfigurable channels, enabling both manufacturing test and in‑field diagnostics.

The successful silicon demonstration by Synopsys and TSMC, built on TSMC’s N3P FinFET process and packaged with CoWoS‑S, validates this ecosystem. By accessing a concealed die through a JTAG‑to‑AXI bridge and exercising UCIe links at both 4 Gbps and high‑rate modes, the team proved that comprehensive monitoring, logic testing, and memory BIST can be performed without physical access. This capability reduces test time, lowers pin count, and cuts hardware costs, accelerating time‑to‑market for AI accelerators and safety‑critical chips. As multi‑die adoption expands, such end‑to‑end test and repair solutions will be a decisive factor in achieving reliable, high‑volume production.