Intel Launches Xeon 6+ "Clearwater Forest" Xeon with 288 E-Cores on 18A Process

Key Takeaways

• 288 efficiency cores on single socket
• Uses Intel 18A, 3, and 7 process nodes
• Supports DDR5‑8000, 96 PCIe 5.0 lanes
• Targets 6G RAN AI inference workloads
• Enables up to 576 cores in dual‑socket servers

Summary

Intel unveiled the Clearwater Forest Xeon 6+ at MWC, a chiplet‑based server processor that combines twelve 18A compute tiles with Intel 3 and Intel 7 base and I/O tiles. The design delivers up to 288 Darkmont efficiency cores and more than 1 TB of last‑level cache on a single socket, scaling to 576 cores in a dual‑socket system. It supports DDR5‑8000 memory, 96 PCIe 5.0 lanes and 64 CXL 2.0 lanes, targeting high‑density AI inference and vRAN workloads. Intel positions the chip as a single‑silicon solution for 6G edge computing and cloud virtualization.

Pulse Analysis

Intel’s Clearwater Forest Xeon 6+ pushes the envelope of server‑grade density by marrying twelve 18A compute chiplets with three Intel 3 base tiles and two Intel 7 I/O tiles in a sophisticated 2.5 D/3D stack. Each compute tile houses six modules of four Darkmont efficiency cores, delivering 24 E‑cores per tile and a staggering 288 E‑cores on a single socket, with a package‑level L3 cache exceeding one gigabyte. The high‑bandwidth on‑chip fabric and Foveros Direct 3D stacking ensure low‑latency communication across the heterogeneous tiles.

The architecture is purpose‑built for the emerging 6G and edge‑AI landscape, where network operators need to host virtualized RAN (vRAN) functions and on‑site inference without relying on separate accelerators. By integrating matrix and vector extensions, 12 memory channels, DDR5‑8000 bandwidth, 96 PCIe 5.0 lanes and 64 CXL 2.0 lanes, Clearwater Forest can handle control‑plane, user‑plane and AI workloads on a single silicon platform. This consolidation reduces system complexity, cuts latency, and aligns with operators’ push toward power‑efficient, real‑time processing at the cell level.

For hyperscale cloud providers, the ability to spin up hundreds of virtual machines from a dual‑socket system translates into higher VM density and better price‑performance ratios. The massive core count, combined with a large shared cache, excels at workloads that consist of many small, parallel inference tasks, such as video transcoding or micro‑service architectures. While AMD’s EPYC and ARM‑based offerings continue to challenge Intel’s market share, the Clearwater Forest’s chiplet heterogeneity and support for emerging standards position it as a compelling option for data centers seeking future‑proof scalability.