Digital Design & Comp. Arch: L15: Dataflow, Superscalar Execution & Branch Prediction (Spring 2026)
Why It Matters
Understanding dataflow, superscalar pipelines, and branch prediction is essential for building faster, more power‑efficient processors while addressing emerging security and memory‑bandwidth challenges that dominate today’s silicon roadmap.
Key Takeaways
- •Dataflow models enable fine‑grained parallelism beyond traditional pipelines
- •Superscalar CPUs issue multiple instructions per cycle, boosting throughput
- •Accurate branch prediction reduces pipeline stalls, improving performance
- •Processing‑in‑memory research tackles the memory‑wall bottleneck
- •RowHammer highlights security risks in dense DRAM designs
Pulse Analysis
The ETH Zürich lecture series continues to set a benchmark for computer‑architecture education, and Lecture 15 zeroes in on three pillars of modern CPU design: dataflow, superscalar execution, and branch prediction. Dataflow architectures break the rigid fetch‑decode‑execute sequence, allowing operations to fire as soon as operands arrive, which is especially valuable for workloads with irregular memory access patterns. Superscalar pipelines extend this concept by dispatching multiple independent instructions each cycle, demanding sophisticated scheduling and dependency tracking to avoid hazards.
Superscalar and dataflow ideas converge with the rising interest in processing‑in‑memory (PIM) and memory‑centric computing, topics highlighted in the recommended readings. By moving compute closer to DRAM, PIM mitigates the long‑standing memory wall that limits traditional von Neumann designs. Researchers like Prof. Mutlu have shown that integrating simple arithmetic units within DRAM can accelerate data‑intensive tasks—ranging from database queries to genome analysis—while reducing energy per operation. This synergy underscores why academic curricula now blend classic micro‑architectural techniques with emerging memory technologies.
Branch prediction, the third focus of the lecture, remains a critical performance lever. Modern predictors employ hybrid schemes, leveraging global and local history to forecast the direction of conditional branches with over 99% accuracy. However, the same speculative execution mechanisms that enable high prediction rates have exposed security vulnerabilities, exemplified by the RowHammer phenomenon and speculative‑execution attacks. By coupling rigorous predictor design with security‑aware memory architectures, the next generation of processors can achieve both speed and resilience, a balance that ETH Zürich’s program aims to instill in its students.
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