Digital Design & Comp. Arch: L22: Memory Hierarchy and Caches (Spring 2026)
Why It Matters
Choosing the right memory tier determines data‑center efficiency and product competitiveness, as latency, power, and density directly impact performance and total cost of ownership.
Key Takeaways
- •Memory hierarchy balances speed, cost, density, and energy consumption.
- •DRAM offers high density but requires refresh and has higher latency.
- •SRAM provides fast, non‑volatile access but is expensive and low density.
- •Phase‑Change Memory (PCM) delivers higher density with slower performance.
- •Emerging memories like Intel Optane reshape system design despite integration challenges.
Summary
Lecture 22 of the Digital Design & Computer Architecture course examines the memory hierarchy and cache architectures, reviewing how different memory technologies—SRAM, DRAM, and emerging non‑volatile options—fit into a multi‑level system.
The instructor stresses that each level trades speed, capacity, cost, and energy. SRAM cells are fast and refresh‑free but consume more transistors, making them expensive and low‑density; DRAM achieves high density with a 1T‑1C cell but incurs refresh overhead, longer latency, and separate manufacturing processes. Phase‑Change Memory offers superior scalability and multi‑bit storage, yet its write‑and‑reset cycles introduce higher latency and energy.
Examples include DRAM’s need to refresh every tens of milliseconds, SRAM’s use in on‑chip caches, and Intel’s 3D XPoint‑based Optane DIMMs delivering 128 GB per module. The lecture also cites research replacing DRAM with PCM or building hybrid DRAM‑PCM systems to balance performance and capacity.
For architects, understanding these trade‑offs guides cache sizing, memory‑controller design, and decisions about hybrid or persistent memory adoption, directly affecting system throughput, power budgets, and overall cost.
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