Digital Design & Comp. Arch: L4: Sequential Logic Design & Finite State Machines (Spring 2026)
•February 28, 2026
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Why It Matters
Understanding FSMs and synchronous timing is foundational for designing reliable, high‑performance digital hardware, directly impacting future work on Verilog, FPGA prototyping, and real‑world system integration.
Key Takeaways
- •Sequential logic builds on gated D‑latch memory structures
- •Finite State Machines model sequential lock behavior with states
- •Asynchronous machines transition instantly, synchronous use clocked timing
- •Memory arrays use address decoding to read/write multiple bits
- •Upcoming labs will introduce Verilog, timing, and FPGA implementation
Summary
The lecture continued the Digital Design course by completing the discussion of sequential logic and introducing finite state machines (FSMs). After reviewing memory elements—from cross‑coupled inverters to gated D‑latches and multi‑bit memory arrays—the professor emphasized the need for storage elements that can remember past inputs, setting the stage for state‑based design. Key insights included the distinction between combinational and sequential systems, illustrated with a combination‑lock example that required a specific input sequence to transition through states A, B, C, and D before unlocking. The instructor highlighted how FSMs capture these transitions, and explained that the lock operates as an asynchronous machine, reacting immediately to inputs, whereas modern computers favor synchronous designs that rely on a clock to coordinate state changes and ensure reliable timing. Notable details featured a practical discussion of extra‑credit policy (a 1% grade boost), the hardware cost growth from a four‑transistor inverter to a 20‑transistor gated latch, and the upcoming lab focus on Verilog, timing analysis, and FPGA prototyping. Student questions clarified the lock’s behavior and the difference between asynchronous and synchronous state transitions. The implications are clear: mastering FSM design and timing concepts is essential for building reliable digital systems, and the forthcoming labs will provide hands‑on experience with hardware description languages and real silicon implementation, preparing students for industry‑level digital design challenges.
Original Description
Digital Design and Computer Architecture, ETH Zürich, Spring 2026 (https://safari.ethz.ch/ddca/spring2026/)
Lecture 4: Sequential Logic Design & Finite State Machines
Lecturer: Prof. Onur Mutlu
Date: 27 February 2026
Lecture 4 Slides (pptx): https://safari.ethz.ch/ddca/spring2026/lib/exe/fetch.php?media=onur-ddca-2026-lecture4a-sequential-logic-ii-beforelecture.pptx
Lecture 4 Slides (pdf): https://safari.ethz.ch/ddca/spring2026/lib/exe/fetch.php?media=onur-ddca-2026-lecture4a-sequential-logic-ii-beforelecture.pdf
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From Molecules to Genomic Variations: Accelerating Genome Analysis via Intelligent Algorithms and Architectures
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