Digital Design & Computer Architecture D8: Problem-Solving Session 8 (Spring 2026)

Onur Mutlu Lectures
Onur Mutlu LecturesApr 27, 2026

Why It Matters

Mastering out‑of‑order execution and tag‑based dependency handling is critical for building faster processors and for students to solve complex architecture problems accurately.

Key Takeaways

  • Out-of-order execution reduces stalls via register renaming effectively.
  • Reorder buffer and reservation stations manage tags and data flow.
  • Thomas algorithm illustrates tag broadcasting and dependency resolution in pipelines.
  • Execution units have distinct pipelines and reservation capacities affecting throughput.
  • Snapshot analysis maps tags to architectural registers for debugging.

Summary

The session focused on out‑of‑order execution and Thomas’s algorithm, reviewing how modern pipelines mitigate data dependencies through register renaming and dynamic scheduling. The instructor recapped lecture concepts before tackling a common exam problem that requires reverse‑engineering the Thomas algorithm from a given processor state. Key insights included the role of the reorder buffer in assigning tags, the function of reservation stations as holding buffers, and the broadcast mechanism that updates dependent instructions once a result is produced. Detailed examples showed how a write‑after‑read hazard on R3 can be avoided by renaming to R6, and how tags such as C and A propagate through the common data bus to enable subsequent instructions to fire without stalling. Notable excerpts highlighted the mapping of tags to architectural registers (e.g., tag L ↔ R8, tag F ↔ R5) and the snapshot of the reservation stations and register alias table used to construct a data‑flow graph. The instructor emphasized the importance of tracking valid bits, tag deallocation after write‑back, and the separate output buses for the adder and multiplier. Understanding these mechanisms is essential for designing high‑throughput CPUs and for students preparing for architecture exams, as they illustrate how out‑of‑order dispatch, register renaming, and precise state tracking collectively boost pipeline efficiency.

Original Description

Digital Design and Computer Architecture, ETH Zürich, Spring 2026 (https://safari.ethz.ch/ddca/spring2026/)
D8: Problem-Solving Session 8
Lecturer: Prof. Onur Mutlu
Date: 27 April 2026
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