Digital Design & Computer Architecture - Lecture 23: Memory Hierarchy and Caches (Spring 2022)
Why It Matters
These technology trade-offs directly shape processor architecture, system performance, and storage design; emerging nonvolatile memories could upend conventional memory hierarchies and enable new system-level optimizations. Understanding the limits of each memory type is essential for architects and businesses planning for future compute and storage products.
Summary
The lecture reviewed fundamentals of memory organization and the design of memory hierarchies and caches, emphasizing why SRAM is used for on-chip caches while DRAM serves as main memory due to differing fabrication and capacitor requirements. It surveyed memory technologies — DRAM, SRAM, flash, phase-change (PCM) and emerging resistive memories — highlighting trade-offs such as latency versus density, non-volatility, and endurance constraints. The instructor noted how technologies like flash and PCM can disrupt traditional hierarchies by blurring the line between working memory and storage, and described the complexity of flash-based storage controllers and their internal memory hierarchies. Practical manufacturing and system-design considerations were stressed as key reasons for current architectural choices and potential future shifts.
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