Memory-Centric Computing - Winter School on Operating Systems (WSOS) Opening Talk - 03.04.2023
•February 23, 2026
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Why It Matters
Memory‑Centric Computing promises to overcome the data‑movement bottleneck that limits scaling of AI, analytics, and scientific workloads, reshaping hardware design and industry roadmaps.
Key Takeaways
- •Memory latency dominates modern workloads.
- •Processing-in-memory reduces data movement costs.
- •RowHammer exposes DRAM reliability challenges.
- •Architectures must co-design compute and memory.
- •Industry adopts PIM for AI and genomics.
Pulse Analysis
Memory‑Centric Computing is gaining traction as the industry confronts the "memory wall"—the growing disparity between processor speed and memory access latency. By embedding simple compute units directly within DRAM or emerging non‑volatile memory, processing‑in‑memory (PIM) architectures dramatically cut the number of costly data transfers across the memory bus. This shift not only accelerates latency‑sensitive applications such as real‑time analytics and deep‑learning inference but also slashes energy consumption, a critical factor for data‑center sustainability. Researchers like Prof. Mutlu have demonstrated prototype systems that achieve order‑of‑magnitude speedups on genome‑sequencing and graph‑processing workloads, underscoring the practical benefits of moving computation closer to data.
A key driver behind this movement is the increasing prevalence of security and reliability concerns in conventional DRAM, exemplified by the RowHammer phenomenon. RowHammer reveals how aggressive access patterns can induce bit flips, threatening data integrity. Memory‑Centric designs mitigate such risks by reducing the frequency of row activations and enabling localized error‑correction mechanisms. Moreover, the co‑design of memory and compute opens new avenues for architectural innovation, such as programmable memory controllers that can execute custom kernels, effectively turning memory into a specialized accelerator.
Industry adoption is accelerating, with major silicon vendors and cloud providers investing in PIM‑enabled chips for AI inference, database acceleration, and high‑performance computing. Standards bodies are also exploring interfaces that expose memory‑side compute to software stacks, promising smoother integration for developers. As workloads become more data‑intensive, the economic incentives to lower latency and power draw will push Memory‑Centric Computing from research labs into mainstream production, redefining the balance of compute and storage in future systems.
Original Description
Title: Memory-Centric Computing
Venue: WSOS (Winter School on Operating Systems) Opening Talk
Presenter: Prof. Onur Mutlu
Date: 3 April 2023
Slides (pptx): https://people.inf.ethz.ch/omutlu/pub/onur-WSOS-Talk-MemoryCentricComputing-April-3-2023.pptx
Slides (pdf): https://people.inf.ethz.ch/omutlu/pub/onur-WSOS-Talk-MemoryCentricComputing-April-3-2023.pdf
Recommended Reading:
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A Modern Primer on Processing in Memory
Intelligent Architectures for Intelligent Computing Systems
RowHammer: A Retrospective
Fundamentally Understanding and Solving RowHammer
RECOMMENDED LECTURE VIDEOS & PLAYLISTS:
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Computer Architecture Fall 2021 Lectures Playlist:
Digital Design and Computer Architecture Spring 2021 Livestream Lectures Playlist:
Featured Lectures:
Interview with Professor Onur Mutlu:
The Story of RowHammer Lecture:
Accelerating Genome Analysis Lecture:
Memory-Centric Computing Systems Tutorial at IEDM 2021:
Intelligent Architectures for Intelligent Machines Lecture:
Computer Architecture Fall 2020 Lectures Playlist:
Digital Design and Computer Architecture Spring 2020 Lectures Playlist:
Public Lectures by Onur Mutlu, Playlist:
Computer Architecture at Carnegie Mellon Spring 2015 Lectures Playlist:
Rethinking Memory System Design Lecture @stanfordonline :
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