SRAM Cell Architecture Explained | 6T SRAM Design Basics | VLSI & Memory Design

Why It Matters

Understanding SRAM’s 6T cell operation is essential for engineers designing high‑speed caches, where latency gains outweigh the penalties of increased area and power consumption.

Key Takeaways

• SRAM stores one bit per cell using a 6‑transistor latch, no refresh.
• Word lines select rows; bit lines carry data for read/write operations.
• Write operation: address decoder activates word line, data driven onto bit lines.
• Read operation uses pre‑charge and sense amplifier to detect differential bit‑line voltage.
• SRAM provides latency caches, but uses more area and power than DRAM.

Summary

The video introduces static random‑access memory (SRAM) and explains the classic 6‑transistor (6T) cell architecture used in modern microprocessor caches. It walks through the physical layout of an SRAM array, distinguishing horizontal word lines that select rows from vertical bit lines that carry data, and shows how a three‑bit address decoder activates a specific word line to target a group of cells. Key technical points include the write cycle—where the address decoder raises the appropriate word line, the data is placed on complementary bit lines, and pass transistors (M5, M6) latch the values—and the read cycle, which pre‑charges both bit lines to VDD, activates the word line, and relies on a sense amplifier to detect the voltage differential between bit line and its complement. The presenter also details the cross‑coupled inverter latch that retains state after the word line is released, highlighting SRAM’s volatile nature when power is removed. The instructor emphasizes practical examples: a six‑cell block can store six bits simultaneously, and a three‑bit address yields eight possible rows. He demonstrates how the sense amplifier translates the tiny voltage difference into a digital output, and how the pre‑charge circuit ensures consistent read conditions. The discussion of pass transistors acting as switches reinforces the importance of threshold voltage control in reliable operation. Overall, the video underscores SRAM’s speed advantage for L1‑L3 caches, while noting its higher area and power consumption compared to DRAM. Designers must balance these trade‑offs when selecting memory technologies for performance‑critical applications.

Original Description

In this session, we dive deep into the architecture of an SRAM (Static Random Access Memory) cell, one of the most fundamental building blocks in modern digital systems and VLSI design.

You will learn how a typical 6T SRAM cell is structured using cross-coupled inverters and access transistors. We break down the working principle of read and write operations, explain the role of word line and bit lines, and discuss how data is stored reliably in the cell.

This session focuses on building a strong understanding of SRAM architecture, which is essential for anyone interested in memory design, chip design, and VLSI engineering.

Topics Covered:

• Introduction to SRAM

• 6T SRAM Cell Architecture

• Role of Cross-Coupled Inverters

• Access Transistors and Control Signals

• Read and Write Operations

• Importance of Stability in SRAM Design

This video is perfect for students and engineers who want to strengthen their concepts in memory design and digital electronics.

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