Rolling Out the Carpet for Spin Qubits with New Chip Architecture

Why It Matters

QARPET delivers a practical, scalable measurement framework that turns statistical qubit characterization into a tractable engineering problem, accelerating the transition from prototype to commercial quantum computers.

Key Takeaways

• QARPET tiles host two spin qubits plus a charge sensor
• 23×23 array yields over 1,000 qubits with 53 control lines
• Cross‑bar design mimics memory architecture, enabling scalable addressing
• Measured 40 tiles, showing uniform thresholds and low charge noise
• Platform compatible with silicon and Ge/SiGe, supporting automation

Pulse Analysis

Semiconductor spin qubits have long promised high‑density quantum logic, but their path to scale has been hampered by the need to test each device individually. QARPET flips this paradigm by arranging qubits into a modular grid of "tiles," each containing two spin qubits and a charge sensor. The cross‑bar wiring scheme, reminiscent of DRAM memory, lets a single set of row and column lines address any tile without a proportional increase in cryogenic wiring, dramatically simplifying the control infrastructure required for massive arrays.

The first demonstration chip, built on a germanium‑on‑silicon‑germanium heterostructure, showcases a 23 × 23 tile matrix that could accommodate more than a thousand qubits while demanding only 53 control lines. High‑frequency readout of 40 randomly selected tiles confirmed that each unit can be tuned independently, with threshold voltages and charge‑noise levels staying within tight tolerances across the wafer. This statistical uniformity is a critical metric for manufacturing yield, offering engineers concrete data to refine lithography and material growth processes.

Beyond the immediate technical gains, QARPET’s compatibility with standard semiconductor fab lines means it can be transferred to silicon‑based spin‑qubit platforms without major retooling. Coupled with emerging machine‑learning tuning algorithms, the architecture promises rapid, automated calibration of thousands of qubits per cooldown. For investors and industry leaders, the chip signals a tangible step toward the quantum‑computing roadmaps that envision processors with millions of coherent qubits, bridging the gap between laboratory breakthroughs and scalable commercial hardware.