NDSS 2025 – On Borrowed Time – Preventing Static Side-Channel Analysis

Why It Matters

Static side‑channel attacks bypass traditional dynamic defenses, so Borrowed Time offers a vital new layer of hardware security for cryptographic devices.

Key Takeaways

• Static side‑channel attacks target idle circuit states.
• Borrowed Time wipes key data during detected idle periods.
• Countermeasure works on FPGA implementations, even masked designs.
• Demonstrated resistance to power SCA, LLSI, and impedance analysis.
• Requires continuous monitoring, minimal performance impact.

Pulse Analysis

The security community has long focused on dynamic side‑channel attacks that harvest information during active computation, but a newer class of static attacks is gaining traction. Techniques like static power analysis, laser logic state imaging, and impedance analysis exploit the electrical or optical signatures of a chip while it sits idle, allowing attackers to extract cryptographic keys with low noise and high precision. Existing countermeasures, designed for dynamic leakage, often fail to address this dormant exposure, creating a gap that threatens hardware‑based security across IoT, automotive, and critical infrastructure sectors.

Borrowed Time tackles the problem by embedding a watchdog that watches for idle conditions and instantly overwrites any key‑dependent data stored in unprotected flip‑flops or registers. The method leverages the observation that static attacks require the secret to remain unchanged for a measurable interval; by shortening or eliminating that window, the attack surface collapses. Implemented on FPGAs, the approach integrates seamlessly with existing design flows and adds only marginal latency, while preserving the functionality of masked implementations. Experimental results show that a previously vulnerable masked AES core becomes resistant when Borrowed Time is active, confirming the technique’s effectiveness against multiple static leakage modalities.

For industry, the emergence of Borrowed Time signals a shift toward proactive hardware hygiene, where continuous state monitoring becomes a standard design practice. Adoption will likely accelerate in sectors where physical access is a realistic threat, such as smart cards, secure elements, and edge devices. Moreover, the concept opens avenues for further research into low‑overhead idle detection and automated data sanitization, potentially influencing future standards for side‑channel resilience and reinforcing the overall trustworthiness of cryptographic hardware.