Finding Hardware Bugs - Computerphile

Why It Matters

Undetected EDA tool bugs can corrupt silicon designs, leading to costly respins and security risks; formal verification promises provable correctness, safeguarding the hardware supply chain.

Key Takeaways

• Researchers systematically fuzz hardware designs to expose EDA tool bugs.
• Place-and-route tools can incorrectly remove logic, causing functional errors.
• Dynamic lookup tables expose subtle bugs missed by static analysis.
• Formal verification aims to mathematically prove EDA tool correctness.
• Verified synthesis and equivalence checkers could reduce reliance on fuzzing.

Summary

The video explores how researchers are improving the reliability of electronic design automation (EDA) tools, which translate human‑readable hardware specifications into the bitstreams that configure chips such as FPGAs. By focusing on the place‑and‑route stage, the team demonstrates that even mature commercial tools can introduce subtle bugs that corrupt the intended functionality of a design.

To uncover these flaws, the researchers built a fuzzing framework that generates thousands of random, yet syntactically valid, hardware netlists. Each netlist is fed through the target place‑and‑route tool and then compared to the original using an equivalence checker. When the checker flags a mismatch, the team isolates a minimal circuit that still triggers the error and files a bug report with the vendor. One concrete example involved a dynamic lookup table where the tool incorrectly eliminated an inverter, assuming the table’s contents were static, leading to incorrect behavior once the table was re‑programmed at runtime.

The discussion also highlights a longer‑term strategy: formal verification of EDA tools. By constructing mathematical proofs—using proof assistants such as Lean, Coq, or Isabelle—researchers aim to guarantee that synthesis and equivalence‑checking tools preserve design semantics for all possible inputs. The speaker notes ongoing projects to build a verified synthesis flow and a verified equivalence checker, suggesting that rigorous proof techniques could eventually replace ad‑hoc fuzzing.

If successful, these efforts would dramatically reduce costly silicon respins and security vulnerabilities stemming from tool‑induced bugs. Verified EDA pipelines would give chip designers confidence that the compiled netlist faithfully implements their specifications, accelerating time‑to‑market and enhancing the overall trustworthiness of hardware ecosystems.

Original Description

When you're setting your hardware design out using automated tools is essential, but what if the tools themselves have bugs in them? John P Wickerson is based at Imperial College London.

The paper that John's team wrote about the work: https://johnwickerson.github.io/papers/fuzzing_pnr.pdf

An accessible blogpost John wrote about the work: https://johnwickerson.wordpress.com/2026/01/06/finding-bugs-in-fpga-place-and-route-tools/

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This video was filmed and edited by Sean Riley.

Computerphile is a sister project to Brady Haran's Numberphile. More at https://www.bradyharanblog.com