Show HN: An LLM-Powered PCB Schematic Checker (Major Update)

Why It Matters

By catching datasheet‑level errors before fabrication, Traceformer reduces costly respins and accelerates hardware time‑to‑market, addressing a critical gap in traditional ERC/DRC workflows.

Key Takeaways

• AI catches schematic errors before fabrication
• Parallel agents speed up subsystem analysis
• Evidence cites specific datasheet pages
• Supports OpenAI and Anthropic models
• Free tier enables risk‑free testing

Pulse Analysis

The electronic design cycle has long relied on rule‑check tools that verify connectivity and clearance but often miss application‑level oversights such as component rating mismatches or undocumented dependencies. As product timelines shrink, a single schematic mistake can trigger costly respins and delay market entry. Recent advances in large language models now allow engineers to query datasheets and design intent directly, turning static documentation into actionable verification. This shift creates an opportunity for AI‑driven checks that complement, rather than replace, traditional ERC and DRC processes.

Traceformer implements this vision with a three‑phase, multi‑agent pipeline. The Planner parses KiCad or Altium netlists, isolates subsystems, and generates evidence requests. Up to ten Worker agents operate in parallel, each pulling specifications from relevant datasheets and applying lightweight LLMs to assess compliance. The Merger consolidates these findings into a structured report that flags errors, warnings, and missing information, always citing the exact datasheet page as proof. Users can select OpenAI or Anthropic models and adjust token limits to balance accuracy and cost.

For hardware firms, the tool promises measurable savings by eliminating preventable fab failures and reducing engineering rework. Transparent, usage‑based pricing means startups and large OEMs alike can scale verification without upfront licensing fees. Moreover, Traceformer’s strict data‑privacy stance—using designs only for analysis and never for model training—addresses a common barrier to AI adoption in IP‑sensitive environments. As more designers integrate LLM‑enhanced checks into their workflows, the industry is likely to see a new standard for pre‑fabrication validation, accelerating time‑to‑market while preserving design integrity.