Imec Demonstrates the First 3D Implementation of a Charge Coupled Device for AI Memory Applications

Why It Matters

The 3‑D CCD offers a cost‑effective, high‑density alternative to DRAM for AI, enabling block‑level data access via CXL and potentially easing memory bottlenecks.

Key Takeaways

• First functional 3‑D CCD memory demonstrated with IGZO channel
• >4 MHz charge transfer speed across 80‑120 nm vertical holes
• Compatible with 3‑D NAND flash process for low‑cost scaling
• Designed as CXL® type‑3 buffer, suited for AI block workloads
• Unlimited endurance, long retention, low‑voltage operation highlighted

Pulse Analysis

Artificial‑intelligence models are consuming memory at a rate that outpaces traditional DRAM scaling, forcing the industry to explore new architectures. While DDR‑based DRAM struggles to keep cost‑per‑bit on a downward trajectory, emerging interconnect standards like Compute Express Link (CXL) enable shared memory pools that can be populated with non‑volatile, block‑addressable technologies. This shift creates a market opening for memory solutions that deliver higher density, lower power and endurance far beyond conventional SRAM or DRAM, especially for inference and training workloads that process massive data blocks.

Imec’s 3‑D charge‑coupled device leverages an indium‑gallium‑zinc‑oxide (IGZO) channel to move charge packets vertically through a stack of three word‑lines, mimicking the punch‑and‑plug approach used in 3‑D NAND flash. The device’s 80‑120 nm vertical holes and >4 MHz transfer rate demonstrate that charge‑based storage can be fabricated with existing NAND infrastructure, dramatically reducing capital expenditures. IGZO’s wide bandgap provides low‑voltage operation, long data retention and virtually unlimited write endurance, addressing the wear‑out concerns that plague many emerging memories. By storing data in blocks rather than bytes, the CCD aligns naturally with CXL type‑3 buffer specifications, delivering the high‑bandwidth, low‑latency access AI accelerators demand.

If adopted, Imec’s 3‑D CCD could reshape the memory hierarchy for AI systems, offering a scalable, cost‑effective bridge between DRAM and storage-class memory. Its compatibility with established NAND fabs accelerates time‑to‑market, while the promise of unlimited endurance and block‑level access positions it as a compelling alternative to HBM for large‑scale training clusters. Imec’s €1.2 billion (≈ $1.3 billion) 2025 revenue underscores its capacity to partner with chipmakers and drive volume production, potentially redefining memory economics in the next generation of AI hardware.