Reductive Transformation of ALD TeO2 Into Continuous and Impurity‐Free Tellurium Films

Why It Matters

By delivering ultrathin, high‑quality p‑type tellurium films, the method unlocks new pathways for back‑end‑of‑line integration and accelerates the adoption of 3D stacked architectures that demand low‑temperature processing and superior hole mobility.

Key Takeaways

• Continuous Te films achieved below ~5 nm thickness.
• In‑situ TeH₂ reduction removes oxygen from bulk and interface.
• Process is self‑limiting, preserving conformality in high‑aspect structures.
• Resulting transistors show low contact resistance and stable switching.
• Enables low‑temperature p‑type integration for 3D monolithic chips.

Pulse Analysis

The semiconductor industry has long grappled with a shortage of high‑performance p‑type channel materials that can be deposited at temperatures compatible with back‑end‑of‑line (BEOL) processes. While tellurium offers exceptional hole mobility, conventional atomic‑layer deposition (ALD) yields discontinuous, island‑like films due to weak surface adhesion, limiting its utility in advanced node devices. This material gap has constrained the scaling of monolithic 3D integration, where both n‑type and p‑type layers must coexist without compromising thermal budgets.

The newly reported reductive transformation sidesteps these limitations by first depositing a conformal TeO₂ template via ALD, then converting it to elemental Te through a TeH₂‑mediated reduction using Te(SiMe₃)₂ and NH₃. The reaction is self‑limiting, ensuring complete oxygen removal from the film’s bulk and its interface with underlying dielectrics. Crucially, the process maintains the original ALD conformality, enabling uniform coverage in high‑aspect‑ratio structures and delivering continuous crystalline Te even at thicknesses below approximately 5 nm. This impurity‑free, ultrathin layer exhibits low contact resistance and robust electrical stability across planar and non‑planar transistor geometries.

For manufacturers, the technique offers a practical route to integrate p‑type chalcogenide channels into BEOL stacks without exceeding temperature constraints, thereby expanding the material palette for 3D stacked logic and memory. The ability to produce reliable, low‑resistance Te contacts could improve device performance, reduce power consumption, and accelerate the rollout of heterogeneous integration strategies. As the industry pushes toward ever‑denser architectures, such chemically driven film engineering is poised to become a cornerstone of next‑generation semiconductor fabrication.