Unified Steep‐Slope Switching and Non‐Volatile Memory in a Complementarily Stabilized Van Der Waals Ferroelectric Transistor

Why It Matters

By unifying ultra‑low‑power switching and persistent storage, the FeNC‑FET paves the way for compact logic‑in‑memory architectures that can dramatically cut energy consumption in edge and data‑center processors.

Key Takeaways

• FeNC-FET achieves sub‑60 mV/dec switching and non‑volatile memory
• CIPS/h‑BN/α‑In₂Se₃ stack provides complementary negative‑capacitance and bistability
• Device shows 35 mV/dec forward, 51 mV/dec reverse sub‑threshold swing
• Memory window ~3 V, retention >10⁴ s, >2500 program‑erase cycles
• Demonstrates AND, OR, majority logic‑in‑memory with 10 µs pulses

Pulse Analysis

The race for ultra‑low‑power electronics has long been hampered by a trade‑off between steep‑slope transistors and non‑volatile memory. Conventional negative‑capacitance FETs (NC‑FETs) suppress ferroelectric hysteresis to achieve sub‑thermal sub‑threshold swings, while ferroelectric FETs (Fe‑FETs) embrace bistability for data storage, leaving designers to choose one capability at the expense of the other. This dichotomy limits the density and energy efficiency of emerging logic‑in‑memory systems, especially as Moore’s Law slows and heterogeneous integration becomes essential.

The FeNC‑FET breakthrough stems from a carefully engineered van der Waals heterostructure that layers CIPS, hexagonal boron nitride, and α‑In₂Se₃. CIPS contributes a static negative curvature in its energy landscape, effectively acting as a voltage‑amplifying capacitor. The atomically thin h‑BN interlayer mitigates charge leakage and stabilizes the interface, while α‑In₂Se₃ retains a robust, switchable polarization that encodes binary states. This cooperative mechanism enables sub‑60 mV/dec switching without sacrificing a clear memory window, delivering performance metrics—35 mV/dec forward swing, 3 V window, >10⁴ s retention—that rival or exceed the best of each separate technology.

From a market perspective, integrating steep‑slope logic and non‑volatile storage in a single transistor could reshape processor design for AI accelerators, IoT edge nodes, and neuromorphic chips. The demonstrated logic‑in‑memory operations with microsecond pulses suggest that complex Boolean functions can be executed directly within the memory fabric, slashing data movement overheads and power draw. As the semiconductor industry seeks to extend scaling through 3D stacking and heterogeneous integration, the FeNC‑FET offers a compact, CMOS‑compatible building block that may accelerate the adoption of energy‑frugal computing platforms.