2D Transistor Goes Narrower

Why It Matters

Sub‑100 nm 2D transistors could extend Moore’s‑law scaling beyond silicon, enabling faster, more energy‑efficient chips for next‑generation computing and flexible electronics.

Key Takeaways

• Sub‑100 nm MoS₂ nanoribbon channels demonstrated with high performance
• LELE lithography‑etch sequence achieves precise width control
• Carrier mobility remains comparable to wider ribbons despite scaling
• Enables continued Moore’s‑law scaling using atomically thin 2D materials
• Potential for low‑power, flexible electronics and heterogeneous integration

Pulse Analysis

The breakthrough centers on MoS₂ nanoribbons fabricated through a LELE (litho‑etch‑litho‑etch) process that delivers sub‑100 nm channel widths while preserving high carrier mobility. By carefully alternating lithography and etching steps, the researchers achieved uniform ribbon dimensions and minimized edge roughness, a common source of scattering in ultra‑narrow channels. Mobility measurements show only a modest decline as width shrinks, suggesting that the intrinsic properties of the 2D crystal dominate transport even at the nanoscale. This level of control positions MoS₂ and similar transition‑metal dichalcogenides as viable candidates for post‑silicon scaling.

From a market perspective, the ability to produce reliable, high‑performance 2D transistors addresses a critical bottleneck in the semiconductor roadmap. As silicon approaches its physical limits, manufacturers are seeking alternatives that can deliver higher drive currents and lower leakage without incurring prohibitive cost. The demonstrated LELE technique aligns with existing photolithography infrastructure, easing the transition for fab lines and reducing the capital expenditure typically associated with novel materials. Consequently, chipmakers could adopt 2D channels in heterogeneous integration schemes, pairing them with conventional silicon logic to boost overall system efficiency.

Looking ahead, the research opens avenues for flexible and wearable electronics where thin, bendable substrates are essential. Continued optimization of contact engineering and dielectric integration will be key to unlocking the full potential of 2D nanoribbon devices. Moreover, extending the approach to other layered semiconductors—such as WS₂ or black phosphorus—could broaden the performance envelope, offering designers a richer palette of electronic properties. As the industry grapples with power constraints and the demand for ever‑smaller form factors, these ultra‑narrow 2D transistors are poised to become a cornerstone of next‑generation hardware.