Direct Write, Read, and Erase of a Vertical Heterostructure of Graphene–Monolayer Electrolyte–H‐BN Using Electric Force Microscopy

Why It Matters

The ability to program graphene charge from underneath using a molecular‑thin electrolyte offers a scalable route to ultra‑dense, low‑power memory and logic devices, advancing 2D‑material integration for future nanoelectronics.

Key Takeaways

• Monolayer electrolyte placed between graphene and h‑BN.
• Bistable ions enable non‑volatile doping of graphene.
• Doping density reaches 5 × 10¹² cm⁻².
• EFM writes, reads, erases with 12 nm resolution.
• Retention persists over 25 minutes after voltage removal.

Pulse Analysis

Electric double‑layer (EDL) gating has become a cornerstone for tuning carrier concentrations in two‑dimensional crystals, yet conventional approaches deposit the electrolyte on top of the active layer, limiting spatial control and scalability. By inserting a monolayer‑thick electrolyte between hexagonal boron nitride (h‑BN) and graphene, the new architecture decouples the gating medium from the channel surface, enabling ion migration from either side of the stack. This vertical configuration preserves the pristine nature of the graphene surface while granting unprecedented access to sub‑10‑nanometer electrostatic modulation.

The study leverages electric force microscopy (EFM) not only as a diagnostic tool but also as a nanoscale write‑read‑erase instrument. Ions within the confined electrolyte exhibit bistability, allowing them to be driven toward either the graphene or h‑BN interface and remain locked after the external field is removed. The resulting graphene doping reaches approximately 5 × 10¹² cm⁻², with more than half of the charge retained for over 25 minutes, demonstrating true non‑volatile behavior. Moreover, the EFM mapping achieves a 12 × 12 nm resolution, highlighting the technique’s capability to pattern charge domains at a scale compatible with emerging quantum and neuromorphic devices.

From a commercial perspective, this approach could redefine the roadmap for 2D‑material‑based memory and logic. The nanometer‑resolution ion‑gating eliminates the need for bulky gate dielectrics, reducing device footprint and power consumption. While challenges such as long‑term stability, large‑area uniformity, and integration with existing CMOS processes remain, the proof‑of‑concept establishes a versatile platform for ultra‑dense, reconfigurable electronics that could accelerate the adoption of graphene and other van‑der‑Waals materials in next‑generation computing architectures.