Graphene-Based Sliding Ferroelectric Transistor Stores 3,024 Stable Polarization States

Why It Matters

The massive multi‑level capability dramatically improves weight resolution in neuromorphic processors, reducing synapse count and energy consumption. It also demonstrates scalable, room‑temperature 2D ferroelectric memory for future brain‑inspired chips.

Key Takeaways

• 3,024 stable states achieved via graphene/hBN moiré superlattice
• Non‑volatile retention exceeds 100,000 seconds, projected 10‑year life
• 36 polarization × 84 doping levels multiply state density
• 93.5% neural‑network accuracy matches floating‑point baseline
• Atom‑thin design enables dense integration in neuromorphic chips

Pulse Analysis

The resurgence of two‑dimensional materials has opened new pathways for non‑volatile memory beyond traditional perovskite ferroelectrics. Sliding ferroelectricity, first observed in multilayer hBN and 3R‑MoS₂, exploits minute relative displacements between atomically thin layers to toggle out‑of‑plane polarization without the need for bulky electrodes. By integrating a monolayer graphene channel with hexagonal boron nitride, the Nanjing University team leverages the intrinsic high mobility of graphene and the ultra‑flat hBN surface to create a van der Waals heterostructure where ferroelectric domains can be precisely manipulated at room temperature.

The key innovation lies in the moiré superlattice formed by a 1.8 % lattice mismatch, which generates a long‑wavelength periodic potential that localizes charge carriers injected by source‑drain pulses. This localization yields 36 quasi‑continuous polarization states; adding a gate voltage that sweeps the graphene Fermi level across 84 discrete doping points multiplies the accessible configurations to 3,024 distinct, non‑volatile levels. Retention measurements demonstrate stability for more than 100,000 seconds, and modeling suggests decade‑long endurance, surpassing the ≤32 levels typical of earlier room‑temperature ferroelectric neuromorphic elements.

From a systems perspective, the expanded state space translates directly into higher weight granularity for analog synapses, allowing deep neural networks to retain floating‑point accuracy while using far fewer physical devices. The atom‑thin profile and planar fabrication are compatible with existing semiconductor back‑end processes, promising dense, low‑power neuromorphic arrays that could replace conventional SRAM‑based weight storage. As industry pushes toward brain‑inspired accelerators, graphene/hBN sliding ferroelectric transistors offer a scalable route to integrate memory and logic, accelerating the transition from prototype to commercial AI hardware.