Low Temperature MOCVD Synthesis of High‐Mobility 2D InSe

Why It Matters

The ability to grow uniform, high-mobility InSe at low temperatures unlocks wafer-scale production for next-generation high-speed transistors and photodetectors, addressing a key bottleneck in 2D semiconductor manufacturing.

Key Takeaways

• Low-temp MOCVD yields wafer-scale phase‑pure 2D InSe.
• Optimized Se/In ratio controls In‑rich to Se‑rich phases.
• Epitaxial InSe shows visible absorption and high electron mobility.
• Growth on c‑plane sapphire enables uniform layer orientation.
• Phase diagram guides reproducible synthesis for device integration.

Pulse Analysis

The surge of two‑dimensional semiconductors over the past decade has been driven by their exceptional carrier transport and tunable band gaps. Among them, indium selenide (InSe) stands out for its intrinsic high electron mobility—exceeding 10,000 cm² V⁻¹ s⁻¹ in bulk—and a band gap that can be engineered from 1.25 eV to 2.8 eV as the material thins. Despite these advantages, reliable synthesis of phase‑pure InSe has remained elusive because the In–Se binary system hosts multiple competing compounds, making conventional vapor‑phase techniques prone to defects and compositional drift.

The new study leverages metal‑organic chemical vapor deposition (MOCVD), a process already mature in silicon and compound‑semiconductor manufacturing, to overcome these hurdles. By depositing precursors on c‑plane sapphire at temperatures well below 400 °C and finely tuning the Se‑to‑In ratio, the researchers constructed a comprehensive phase diagram that spans In‑rich, stoichiometric, and Se‑rich regimes. Raman spectroscopy, atomic‑force microscopy, and in‑plane X‑ray diffraction confirmed epitaxial alignment and the absence of secondary phases, while optical absorption measurements revealed strong visible‑range response and electron mobility comparable to exfoliated flakes.

The implications for the semiconductor market are significant. Low‑temperature, wafer‑scale MOCVD of InSe paves the way for integrating this high‑performance 2D material into existing CMOS lines, enabling ultra‑fast transistors, flexible photodetectors, and high‑efficiency solar cells without the thermal budget constraints of traditional epitaxy. Moreover, the documented phase‑space map provides a reproducible recipe for industry partners, reducing trial‑and‑error cycles and accelerating time‑to‑market. Future work will likely focus on heterostructure engineering and scaling the process to larger diameters, cementing InSe’s role in next‑generation electronics.