Study of EUV Nanostructures Using AFM With High-Aspect Ratio Tip (Purdue, Intel, Bruker)

Why It Matters

Accurate EUV metrology is essential for sub‑10 nm chip production; understanding AFM artifacts enables more reliable process control and reduces costly redesigns.

Key Takeaways

• High‑aspect‑ratio diamond tip shows stick‑slip friction on EUV sidewalls
• Random‑forest classifies force curves by linearity, adhesion, hysteresis
• AFM profile inflation stems from tip geometry, photoresist shrinkage, tip bending
• SEM comparison validates AFM artifacts, not measurement superiority
• Findings guide next‑gen AFM tip design for sub‑20 nm lithography

Pulse Analysis

Extreme ultraviolet (EUV) lithography has become the workhorse for manufacturing logic nodes below 10 nm, but its success hinges on precise metrology of photoresist (PR) patterns. Traditional optical scatterometry struggles with three‑dimensional features, prompting fabs to turn to atomic force microscopy for its nondestructive, nanometer‑scale resolution. However, as feature dimensions shrink, the AFM tip itself can become a source of error, especially when probing tall, narrow trenches that approach the tip radius. Understanding these interactions is critical for maintaining yield and avoiding costly mask revisions.

The Purdue‑Intel‑Bruker study tackles this challenge by deploying a high‑aspect‑ratio diamond‑like carbon spike tip and leveraging force‑mapping AFM. Researchers collected thousands of force curves across 40 nm‑pitch EUV structures and fed them into a random‑forest machine‑learning model that sorted the data by linearity, adhesion and hysteresis. The algorithm uncovered a prevalence of stick‑slip friction events and measurable tip bending when the probe engaged PR sidewalls. When the AFM‑derived profiles were cross‑checked against scanning electron microscopy, discrepancies were traced to three factors: electron‑beam‑induced PR shrinkage, geometric dilation from the finite tip size, and the mechanical deflection of the tip itself.

These insights have immediate implications for semiconductor fabs and metrology equipment vendors. Recognizing that a sharper, high‑aspect‑ratio tip does not guarantee accurate sidewall measurement forces a rethink of tip design, calibration routines, and data‑correction algorithms. Incorporating machine‑learning classifiers into routine AFM workflows can flag problematic force curves in real time, improving confidence in critical dimension data. As EUV continues to push patterning limits, such refined metrology will be a decisive factor in achieving the performance and cost targets demanded by next‑generation chips.