Sub‐Nanometer Ferroelectric Tunnel Junctions With Record‐High On‐Current Density Through Synergistic Microwave Annealing and High‐Field Activation

Why It Matters

The breakthrough enables ultra‑fast, low‑voltage read operations essential for scaling cross‑point memory arrays, positioning FTJs as a viable competitor to conventional SRAM and DRAM technologies.

Key Takeaways

• Jon >100 kA cm⁻² achieved at 0.4 V in 0.9 nm FTJ
• Microwave annealing cuts interfacial layer to 0.41 nm
• High-field activation (>15 MV cm⁻¹) stabilizes orthorhombic phase
• Endurance exceeds 10⁸ cycles; retention projected 10 years @85 °C
• Scalable approach avoids added material complexity for dense arrays

Pulse Analysis

Ferroelectric tunnel junctions have long promised ultra‑dense, non‑volatile memory, but their commercial viability has been hampered by insufficient on‑state current density (J_on). Conventional FTJs suffer from a thick interfacial layer and depolarization fields that limit charge transport, especially as device dimensions shrink below a nanometer. The need for high J_on is critical for fast read speeds and robust sensing margins in cross‑point arrays, where each cell must be distinguished reliably amidst millions of neighbors.

The new study tackles these bottlenecks by integrating two complementary strategies: aggressive area scaling to sub‑nanometer dimensions and low‑temperature microwave annealing. Microwave energy selectively reduces the interfacial oxide from 0.94 nm to 0.41 nm, eliminating a major leakage pathway without damaging the ferroelectric film. Simultaneously, applying electric fields above 15 MV cm⁻¹ triggers a phase transition to a stable orthorhombic ferroelectric state, enabling J_on values surpassing 10⁵ A cm⁻² at a modest 0.4 V bias. The resulting devices maintain an on/off ratio greater than 15, survive over 108 write‑erase cycles, and are projected to retain data for a decade at elevated temperatures.

These performance metrics signal a turning point for FTJ memory architectures. By achieving high current density and endurance without introducing exotic materials or complex processing steps, the approach aligns with existing semiconductor manufacturing flows, reducing adoption risk. Industry players targeting next‑generation compute‑in‑memory or neuromorphic platforms can now consider FTJs as a credible alternative to traditional charge‑based memories, especially where area efficiency and low‑power operation are paramount. Continued simulation‑driven optimization may push FTJ scaling toward the ultimate limits, unlocking terabit‑scale memory densities in future chip designs.