How Long Will CAN Stick Around As Rival Networks Speed Up?
Automotive Ethernet is emerging as the backbone for software‑defined vehicles, delivering multi‑gigabit bandwidth, deterministic timing and security that legacy CAN/LIN cannot provide. Yet CAN, LIN and FlexRay persist because they are low‑cost, proven, and deeply embedded in existing ECUs and sensor networks. Industry leaders predict a hybrid transition lasting five to ten years, with Ethernet handling high‑speed domains while legacy buses remain for low‑speed, cost‑sensitive functions. Successful integration will depend on digital twins and system‑level modeling to bridge the two worlds.
Microarchitecture Tailored to 3D-Stacked Near-Memory Processing LLM Decoding (U. Of Edinburgh, Peking U., Cambridge Et Al.)
Researchers from Edinburgh, Peking, Cambridge and other institutions released a paper proposing a new micro‑architecture for 3D‑stacked near‑memory processing (NMP) that targets large‑language‑model (LLM) decoding. By swapping traditional MAC‑tree compute units for a compact, reconfigurable systolic array and leveraging an...
Alumina Nanowires Improve Thermal Management in Advanced Packaging (Georgia Tech Et Al.)
Georgia Tech researchers demonstrated that epoxy composites reinforced with ultralong Al₂O₃ nanowires dramatically improve thermal interface material (TIM) performance for 2.5D/3D semiconductor packaging. At a 28 wt% filler loading, a vertically aligned nanowire architecture achieved 0.78 W/(m·K) out‑of‑plane conductivity—72 % higher than conventional...
When Semiconductor Materials Misbehave
The semiconductor industry’s shift to heterogeneous integration is exposing a widening gap between laboratory‑tested material specs and real‑world production performance. As advanced packaging stacks incorporate dozens of new dielectrics, metals, and polymers, cross‑domain interactions create failure modes that traditional simulation...
Chip Industry Week In Review
Marvell bought Swiss photonics firm Polariton, while Onto Innovation struck a strategic partnership with Rigaku and invested $710 million for a 27% stake. Tesla announced it will be Intel’s first customer for the new 14A process at its Austin Terafab, and...
Blog Review: Apr. 22
The April 22 blog roundup highlights a series of industry podcasts and posts that dissect critical bottlenecks in chip verification, the rising complexity of analog‑mixed‑signal design, and security threats such as ATM jackpotting. It also showcases new verification IP for...
TSV Complexity Leads To Manufacturing Bottleneck
Through‑silicon vias (TSVs) are essential for 3D stacking and high‑bandwidth memory, but shrinking dimensions are driving up fabrication cost and defect rates. The surge in AI demand has strained HBM and advanced‑assembly capacity, creating a bottleneck in the limited pool...
Research Bits: Apr. 21
Researchers at the University of Michigan demonstrated a compute‑in‑memory (CIM) implementation of state‑space models using a 65 nm CMOS resistive‑RAM crossbar, achieving vector‑matrix multiplication within 4.6 bits of the ideal result while dramatically cutting energy use. In Tokyo, scientists from the Institute...
Batteries Charge To The Edge
Breakthrough claims from Finland’s Donut Lab and China’s BYD signal a new era for battery chemistry, promising double‑the‑energy solid‑state cells and ultra‑fast charging that could reach 1,000 km on a single charge. While capacity gains have historically lagged at 4‑8% per...
Emulation-Based SoC Security Verification (U. Of Florida)
University of Florida researchers released a technical paper outlining how hardware emulation can strengthen pre‑silicon security verification for system‑on‑chip designs. The work surveys existing emulation‑based techniques—including assertion checking, coverage‑driven exploration, adversarial testing, information‑flow tracking, fault injection, and side‑channel analysis—and maps...
Panel-Level Packaging’s Second Wave Meets Engineering Reality
Panel-level packaging is gaining traction as wafer‑level economics falter under the growing size of AI and high‑performance computing modules. By switching to rectangular glass or organic panels, manufacturers can increase units per run, spreading fixed costs more efficiently. However, the...
Chiplet Standards Aim For Plug-N-Play
The semiconductor industry is moving beyond basic chiplet interconnects like UCIe and BoW toward a full suite of standards that enable a true plug‑and‑play marketplace. Organizations such as the Open Compute Project, JEDEC, and IEEE are defining specifications for system...
Silicon Photonics Lights The Way To More Efficient Data Centers
Silicon photonics is emerging as a solution to the power‑intensive data‑movement problem in modern data centers, especially as AI workloads generate massive east‑west traffic. By replacing copper with optical links, photonic interconnects can dramatically increase bandwidth density while slashing energy...
EBeam Initiative At SPIE ALP 2026: Continuing Progress On Curvilinear, EUV, And Data Challenges
The eBeam Initiative’s 17th SPIE Advanced Lithography lunch gathered about 150 industry leaders to assess progress on curvilinear masks, EUV adoption, data handling, and multi‑beam mask writers. Speakers highlighted how GPU‑accelerated design and multi‑beam eBeam tools are finally making fully...
Automate And Speed Up TCAD Calibration With Expert Modules And ML Calibration Accelerator
Synopsys has upgraded its Sentaurus Calibration Workbench with expert calibration modules and a new ML Calibration Accelerator, each delivering more than a five‑fold speed increase. The expert modules pre‑build 80% of the workflow, giving TCAD engineers a 5× productivity boost,...