ASE Launches Panel-Level Packaging Line

Key Takeaways

• ASE launches 310mm × 310mm automated panel‑level packaging line.
• Panel format yields up to 96,100 mm² usable area per panel.
• PLP boosts throughput, cuts cost for AI and HPC packages.
• Competitors Samsung, TSMC, Amkor also expanding PLP capabilities.

Pulse Analysis

Panel‑level packaging (PLP) is reshaping the semiconductor assembly landscape by moving from traditional circular wafers to large rectangular substrates. ASE’s new 310 mm × 310 mm line exemplifies this shift, offering a substantial 96,100 mm² usable area per panel. The format enables more dies to be processed simultaneously, slashing per‑die handling time and improving material efficiency—critical factors as AI accelerators and high‑performance computing (HPC) chips grow in size and pin count.

Technically, the ASE line integrates the company’s FOCoS and FOCoS‑Bridge platforms. FOCoS delivers fan‑out chip‑on‑substrate solutions with 2 µm line/space, while FOCoS‑Bridge adds inter‑chiplet routing on tiny silicon pieces, supporting 8 µm line/space. Together, they provide a flexible toolkit for multi‑die architectures that demand high I/O density. By consolidating multiple chips on a single panel, manufacturers can achieve higher throughput, lower cycle times, and reduced packaging costs—advantages that directly address the surge in demand from AI data‑center and HPC workloads.

ASE’s initiative places it among a growing cohort of OSATs, including Samsung, TSMC, Amkor, and Rapidus, that are investing heavily in PLP capacity. This competitive buildup signals a broader industry consensus that PLP will become a cornerstone of advanced packaging for the next generation of compute. For chip designers, the expanding PLP ecosystem promises more options for scaling performance while managing cost, ultimately accelerating time‑to‑market for next‑gen silicon solutions.