Semiconductors Videos

Clock Domain Crossing Using Asynchronous FIFO | Ethernet MAC Controller Design || All About VLSI ||

The video explains clock-domain crossing for an Ethernet MAC controller by contrasting synchronous and asynchronous FIFOs. With a shared clock, a synchronous FIFO safely coordinates write and read pointers and avoids data loss when write and read rates match. When transmitter and receiver run on different clocks or frequencies, the presenter shows why a dual-clock (asynchronous) FIFO is required: writes occur on the high-frequency domain and reads on the low-frequency domain, so separate pointer management and control signals prevent data corruption. The lecture emphasizes write/read enables, pointer increments, and full/empty signalling as core mechanisms for reliable buffering across domains.