CEA-Leti, CEA-List and PSMC Collaborate

Why It Matters

The integration tackles the industry’s bottleneck of data movement and power consumption, unlocking higher AI performance at lower cost. It gives chip designers a ready‑made, energy‑efficient stack that can accelerate time‑to‑market for advanced AI workloads.

Key Takeaways

• RISC‑V IP integrated with silicon photonics for AI chips
• PSMC adds optical links to its 3D stacking platform
• MicroLED GaN solutions boost low‑power optical throughput
• Open‑source processors reduce design cost and increase flexibility
• Collaboration targets energy‑efficient, high‑bandwidth AI compute

Pulse Analysis

The semiconductor sector is confronting a convergence of physical and economic pressures. Traditional copper interconnects are nearing their speed and energy‑efficiency ceiling, while data‑center power budgets tighten and AI workloads demand ever‑greater bandwidth. Engineers are therefore turning to optical communication and open‑source processor architectures as a way to break through these constraints. Silicon photonics promises low‑loss, high‑speed links that consume far less power than electrical traces, and RISC‑V offers a customizable, royalty‑free instruction set that can be tailored to specific AI accelerators.

In this context, CEA‑List, CEA‑Leti and PSMC have formed a joint venture that fuses their core competencies. CEA‑List contributes its mature RISC‑V IP portfolio, enabling designers to embed specialized compute blocks directly into chiplets. CEA‑Leti brings silicon‑photonic foundry expertise and a microLED‑based optical‑link technology that can transmit terabits per second over millimeter‑scale distances with milliwatt‑level power. PSMC supplies its proven 3D‑stacking and interposer platform, creating a heterogeneous integration environment where optical and electronic layers coexist seamlessly.

The partnership positions the three organizations to offer a turnkey solution for next‑generation AI silicon. By delivering a high‑bandwidth, energy‑efficient communication fabric alongside a flexible RISC‑V compute core, they address the key performance‑per‑watt metrics that cloud providers and edge device makers prioritize. Moreover, the use of open‑source IP reduces licensing costs, accelerating time‑to‑market for startups and established OEMs alike. As AI models continue to scale, this integrated photonic‑RISC‑V stack could become a foundational building block for future data‑center and autonomous‑system processors.