CEA-Leti Scales Ferroelectric RAM to 22nm Node

Why It Matters

The breakthrough gives non‑volatile memory the density and speed previously limited to volatile SRAM, enabling on‑chip AI inference that cuts data‑transfer latency and energy use. This could reduce the power draw of billions of edge devices, easing pressure on global electricity consumption.

Key Takeaways

• 3D HZO FeRAM cells 2.5× smaller than SRAM at 22 nm
• Achieves SRAM‑level density of 10 nm node with non‑volatile memory
• Demonstrated wake‑up‑free operation using 17:1 aspect‑ratio capacitors
• Operates at 1.3 V, enabling ultra‑low‑power edge AI
• Path to dense 22 nm FDSOI embedded FeRAM arrays

Pulse Analysis

Ferroelectric RAM (FeRAM) has long been praised for its non‑volatility and low‑power operation, yet its adoption lagged behind volatile SRAM because planar capacitor designs limited cell density. As edge computing workloads grow, designers need memory that can sit close to the processor without inflating die area or power budgets. Traditional scaling approaches hit a physical ceiling: the capacitor footprint, not the transistor, dictated the minimum cell size, preventing FeRAM from competing in high‑performance domains.

CEA‑Leti’s new 3‑D architecture flips that paradigm by building the ferroelectric capacitor vertically using hafnium‑zirconium‑oxide (HZO) thin films. The resulting 1T‑1C bitcells occupy just 0.047 µm² at the 22 nm node—2.5 times smaller than standard SRAM and comparable to SRAM at the much more advanced 10 nm node. Operating at a modest 1.3 V, the cells also eliminate the notorious “wake‑up” instability, thanks to a high‑aspect‑ratio (up to 17:1) design that stabilizes the orthorhombic phase of HZO. These advances were demonstrated in a back‑end‑of‑line (BEOL) process compatible with existing FDSOI platforms, showing a clear migration path for foundries.

The industry impact could be profound. With density on par with SRAM and the inherent non‑volatility of FeRAM, chip designers can embed large memory arrays directly into AI accelerators, reducing the need for frequent DRAM accesses and cutting data‑movement energy. Compared with competing emerging memories such as MRAM or ReRAM, the CEA‑Leti solution offers a compelling blend of speed, power efficiency, and manufacturability. If the roadmap to even finer capacitors materializes, we may see FeRAM become the default embedded memory for edge devices, autonomous systems, and space‑qualified hardware, reshaping the memory hierarchy for the next generation of low‑power computing.