Credo to Unveil AI Interconnect Solutions at TSMC 2026 Symposium

Why It Matters

By alleviating memory and interconnect bottlenecks, Credo’s solutions could accelerate AI inference scaling and reduce power consumption in data centers, giving chip designers a competitive edge.

Key Takeaways

• OmniConnect Weaver uses 112G VSR SerDes for AI inference
• Weaver claims 10× I/O density and up to 20× memory density
• 224G PAM4 SerDes delivers up to 1.6 Tbps aggregate bandwidth
• Credo will showcase solutions at TSMC symposium stops worldwide

Pulse Analysis

The AI hardware landscape is increasingly constrained by memory bandwidth and interconnect latency, factors that can eclipse raw compute power in large‑scale inference models. Credo Technology Group’s partnership with TSMC positions it to address these constraints by leveraging the most advanced 5 nm and 3 nm process nodes. By integrating a lightweight AXI framer with 112 Gbps VSR SerDes, the OmniConnect Weaver aims to reshape how data moves between memory and compute units, delivering density gains that translate into smaller footprints and lower power draw.

Technical depth matters for chiplet‑based architectures and heterogeneous systems that dominate modern AI accelerators. The Weaver’s claimed 10× increase in I/O beachfront density and up to 20× higher memory density represent a substantial leap over conventional LPDDR5X solutions, potentially enabling more aggressive scaling of model parameters without proportional cost hikes. Complementing this, Credo’s 224 Gbps PAM4 SerDes IP, fabricated on TSMC’s 3 nm node, pushes per‑lane throughput to 224 Gbps, aggregating to 1.6 Tbps. Such bandwidth is critical for hyperscale data centers where every terabit per second shaved from the interconnect translates into measurable energy savings and higher overall system throughput.

Credo’s global symposium tour—from Austin to Amsterdam, Shanghai to Yokohama—signals a broader industry shift toward collaborative ecosystem development. As AI workloads continue to dominate cloud and edge compute, vendors that can deliver high‑speed, energy‑efficient interconnects will capture a strategic advantage. The visibility at TSMC’s symposium not only validates Credo’s technology but also highlights the market’s appetite for solutions that treat data movement as a first‑class design pillar, setting the stage for the next generation of AI‑optimized silicon.