DCD-SEMI Introduces eSPI Combo for Next-Generation Intel-Based Platforms

Why It Matters

The combo provides a single, standards‑compliant eSPI solution that cuts design complexity and verification effort, enabling faster, lower‑cost migration from LPC to high‑speed serial interfaces across Intel‑based embedded systems.

Key Takeaways

• DESPI eSPI Combo bundles controller and target IP cores
• Operates up to 66 MHz on single, dual, and quad SPI
• Optimized for Intel platforms, provides LPC‑to‑eSPI migration path
• Technology‑agnostic RTL compatible with all major FPGA and ASIC vendors
• Customizable channels cut area and power, easing qualification

Pulse Analysis

The Enhanced Serial Peripheral Interface (eSPI) has become the de‑facto successor to the aging Low‑Pin Count (LPC) bus in Intel‑based embedded systems. As manufacturers push for higher data rates, lower pin counts, and tighter power envelopes, eSPI’s serial architecture—supporting single, dual, and quad lanes—offers a clear upgrade path. However, integrating both the host controller and peripheral target functions often requires multiple IP blocks, extending design cycles and verification effort. DCD‑SEMI’s new DESPI eSPI Combo addresses this gap by delivering a unified, standards‑compliant solution that streamlines migration from legacy LPC to modern serial interfaces.

The DESPI eSPI Combo pairs a fully configurable controller IP core with a matching target IP, both adhering to the eSPI Base Specification Revision 1.6. Operating at serial clock frequencies up to 66 MHz, the cores support flexible memory‑mapped I/O, virtual‑wire signaling, and optional out‑of‑band channels, giving designers granular control over bandwidth and latency. Delivered as technology‑agnostic RTL, the IP integrates seamlessly into any major FPGA or ASIC flow, allowing teams to enable only required features and thereby minimize silicon area and power consumption. This modularity shortens time‑to‑market while reducing qualification risk.

For system‑on‑chip developers targeting automotive, industrial, and high‑performance embedded markets, the combo offers a low‑risk, cost‑effective route to production. By consolidating controller and target functions into a single, silicon‑proven family, DCD‑SEMI simplifies verification and supports multi‑target architectures common in modern EC designs. The solution’s scalability—from single‑host to complex multi‑slave configurations—positions it well for emerging applications such as edge AI accelerators and advanced sensor hubs. As Intel continues to promote eSPI across its next‑generation CPUs, the DESPI combo is likely to become a standard building block in future SoC portfolios.