Redesigned High-NA Lithography Optical System Aims to Overcome Challenges in Semiconductor Chipmaking

Why It Matters

Cheaper, higher‑resolution EUV tools could accelerate the rollout of denser, more energy‑efficient chips, a critical need for AI‑driven workloads and data‑center sustainability. The breakthrough may reshape the economics of semiconductor manufacturing worldwide.

Key Takeaways

• New high‑NA EUV design targets 2–3 nm feature resolution
• Simulations predict up to 75% cost reduction versus existing EUV tools
• Simpler mirror arrangement could eliminate mask‑3D optical distortions
• Lower power chips may halve data‑center energy use by 2030
• Prototype development at OIST aims for quarter‑price EUV machines

Pulse Analysis

Extreme ultraviolet (EUV) lithography has become the backbone of advanced chip production, yet its high‑numerical‑aperture (high‑NA) variants remain prohibitively expensive, often exceeding $120 million per machine. The technology’s reliance on complex mirror assemblies and mask‑3D optical effects limits yield and drives up operational costs. As semiconductor nodes push below 5 nm, manufacturers face a cost‑performance cliff that threatens the economics of AI accelerators, 5G infrastructure, and next‑gen consumer devices.

Shintake’s proposal reimagines the illumination and projection optics with a streamlined two‑stage mirror configuration—each stage pairing a concave and convex mirror. Optical simulations using OpTaliX indicate that this arrangement can cancel out the distortions that have plagued earlier high‑NA concepts, delivering crisp 2–3 nm patterns while using mirrors that are easier to fabricate and align. The model forecasts up to a 75% reduction in capital expenditure, potentially bringing machine prices down to a quarter of current levels. By simplifying the optical path, the design also promises higher throughput and lower maintenance overhead.

If the prototype validates these claims, the ripple effects could be profound. Denser chips mean shorter interconnects, reducing both power consumption and heat generation—key levers for data‑center operators confronting the International Energy Agency’s forecast of doubled electricity demand by 2030. Lower‑cost, high‑NA EUV tools would democratize access to sub‑3 nm processes, enabling more players to produce AI‑optimized silicon and accelerating the rollout of energy‑efficient hardware. OIST’s next step is building a physical demonstrator, a milestone that could trigger a new wave of investment in semiconductor fabs worldwide.