Simple Coating Could Make Next-Generation Chip Transistors Easier to Manufacture without Damaging Ultrathin Layers

Why It Matters

The technique offers a scalable, low‑damage method for integrating transition‑metal dichalcogenides into semiconductor manufacturing, accelerating the shift to faster, smaller chips beyond silicon’s limits.

Key Takeaways

• Oxygen coating reduces sulfur removal energy to ~14 eV.
• Fluorine coating drops removal energy further to ~10 eV.
• Wider energy window prevents damage to underlying molybdenum layer.
• Chemical assist forms volatile sulfur dioxide, easing atom removal.
• Approach may extend to other TMDs like WS₂ or MoSe₂.

Pulse Analysis

Silicon’s approaching physical limits have spurred intense research into alternative channel materials for transistors, with transition‑metal dichalcogenides (TMDs) such as molybdenum disulfide (MoS₂) emerging as prime candidates. MoS₂ is only three atoms thick—one molybdenum layer sandwiched between two sulfur layers—offering superior electrostatic control and flexibility. However, integrating TMDs with existing silicon processes requires precise removal of the top sulfur layer without compromising the underlying metal, a challenge that traditional plasma etching struggles to meet due to narrow energy margins.

The Princeton team tackled this by applying a thin oxygen or fluorine coating before plasma exposure. Computer simulations showed the coating creates a chemical pathway: incoming ions trigger the formation of sulfur‑oxygen or sulfur‑fluorine molecules that desorb as stable gases, effectively lowering the bond‑breaking energy from ~30 eV to ~14 eV (oxygen) or ~10 eV (fluorine). This expanded energy window gives manufacturers a broader, more forgiving range to strip the sulfur layer cleanly, reducing the risk of inadvertent molybdenum damage. The approach leverages chemistry rather than brute force, turning plasma processing into a selective, low‑impact step.

If adopted at scale, this method could simplify the fabrication of heterogeneous chips that pair silicon with TMD channels, accelerating the rollout of ultra‑dense, high‑performance processors. The lower energy requirements also promise reduced equipment wear and lower operational costs. Future work will assess actual material damage and test the strategy on related TMDs such as tungsten disulfide (WS₂) or molybdenum selenide (MoSe₂), potentially broadening its applicability across the emerging 2‑D semiconductor ecosystem.