The Next 15 Years of Moore’s Law, According to Imec

Why It Matters

CFETs and later 2‑D semiconductors represent the next major leap in transistor scaling, promising higher performance per watt and extending Moore’s Law beyond traditional silicon limits. Their adoption will reshape design, manufacturing and supply‑chain dynamics across the semiconductor industry.

Key Takeaways

• CFETs slated for commercial launch around 2033, halving transistor area
• Intel, Samsung, TSMC have built prototype CFET chips and memory cells
• Imec predicts 2‑D semiconductor channel replacement by 2041 for power savings
• 0.55 NA EUV lithography will enable finer features for A7 node
• CMOS 2.0 will combine stacked dies and fused transistor layers

Pulse Analysis

The complementary FET (CFET) architecture marks a fundamental departure from the planar CMOS paradigm that has dominated for decades. By vertically stacking the PMOS and NMOS transistors, CFETs can achieve roughly a 50% reduction in footprint while preserving—or even enhancing—electrical performance. Industry heavyweights such as Intel, Samsung and TSMC have already produced prototype devices, including ultra‑compact memory cells and ring oscillators, demonstrating the feasibility of the approach. However, the transition demands new process steps, precise silicon‑germanium layering, and advanced etching techniques, all of which Imec is de‑risking through its multi‑year research programs.

Beyond the 2030s, Imec projects a second paradigm shift: replacing the silicon channel in CFETs with atom‑thin, two‑dimensional (2‑D) semiconductors like molybdenum disulfide. These materials can operate at lower voltages due to their sub‑nanometer thickness, delivering substantial power‑per‑watt gains—critical as data‑center and AI workloads push energy budgets. The 2‑D transition, anticipated around 2041, focuses less on density and more on curbing the exponential rise in power consumption, positioning chips to meet stringent efficiency targets without sacrificing compute capability.

Realizing these technologies also hinges on advances in lithography and interconnect packaging. The roadmap calls for 0.55 NA extreme ultraviolet (EUV) tools, which can pattern features finer than today’s 0.33 NA machines, enabling the A7 node’s aggressive dimensions. Simultaneously, wafer‑to‑wafer bonding pitches are shrinking toward 200 nm, supporting millions of vertical interconnects per square millimeter. This convergence of finer patterning, dense 3‑D stacking, and fused transistor layers under the banner of "CMOS 2.0" will empower designers to mix and match process nodes within a single package, unlocking unprecedented performance scaling while extending Moore’s Law into its next era.