Using Graph Attention for Virtual Metrology in Semiconductor Manufacturing (Intel Foundry, ASU)

Why It Matters

Accurate, low‑latency VM reduces reliance on costly physical metrology, accelerating yield optimization in high‑volume fabs. The interpretability of the graph attention model helps engineers pinpoint critical process variables, fostering more efficient manufacturing control.

Key Takeaways

• Graph attention model predicts wafer film thickness from sensor data.
• Outperforms traditional correlation‑driven virtual metrology baselines.
• Captures directional dependencies between process parameters and layer steps.
• Provides interpretable attention weights aligned with physical deposition behavior.
• Enables faster, cost‑effective monitoring for high‑volume semiconductor fabs.

Pulse Analysis

Virtual metrology has become a cornerstone for modern semiconductor fabs seeking to replace slow, expensive physical measurements with rapid, data‑driven predictions. Traditional VM approaches rely heavily on statistical correlations, which often ignore the intricate, time‑varying relationships among thousands of sensor signals generated during deposition. As process nodes shrink to nanometer and angstrom scales, even minor deviations can impact device performance, making precise, real‑time monitoring essential. The emergence of deep learning techniques, particularly those that can model sequential and relational data, offers a path to bridge this gap, but many models still lack transparency for process engineers.

The graph attention‑based framework presented by ASU and Intel introduces a novel way to encode both temporal dynamics and structured dependencies inherent in film deposition. By representing each step‑parameter pair as a node and applying convolutional encoders to extract temporal features, the model builds a rich embedding space. The subsequent parameter‑to‑layer attention layer learns directional influences, allowing each film layer to aggregate the most relevant process information. This architecture not only improves predictive accuracy—surpassing baseline VM models on industrial wafer datasets—but also produces attention weights that map directly to physical process mechanisms, granting engineers interpretable insights into which parameters drive thickness variations.

For the semiconductor industry, the implications are significant. Enhanced VM accuracy reduces the need for frequent in‑line metrology, cutting equipment downtime and material waste while maintaining tight control over critical dimensions. Moreover, the model’s interpretability accelerates root‑cause analysis, enabling faster corrective actions and tighter yield loops. As fabs continue to adopt AI‑enabled control systems, approaches that combine performance with explainability—like graph attention VM—are poised to become integral to next‑generation manufacturing pipelines, supporting the relentless drive toward smaller, faster, and more reliable chips.