Date Rate Calculation || Verilog Coding Techniques Part 16 #allaboutvlsi #vlsi

Why It Matters

Parallel‑to‑serial conversion can quarter throughput, forcing designers to balance bus width, clock speed, and serialization techniques for high‑speed applications.

Key Takeaways

• 100 MHz clock yields 100 M cycles per second continuously.
• Four-bit parallel output gives 400 Mbits/s data rate overall.
• Parallel‑to‑serial (PISO) reduces output to one bit per cycle.
• Serial conversion drops throughput to 100 Mbits/s per second.
• Matching clock frequencies expose parallel vs serial bandwidth differences.

Summary

The video walks through a Verilog‑style calculation of data rates for two simple modules. Module A sends four bits on each rising clock edge at a 100 MHz frequency, while Module B receives the parallel data and converts it to a serial stream using a PISO shift register.

At 100 MHz the clock generates 100 × 10⁶ cycles per second. Multiplying by four bits per cycle gives Module A a throughput of 400 Mbits/s. When the same clock drives Module B, the PISO outputs only one bit per cycle, reducing the effective data rate to 100 Mbits/s.

The presenter emphasizes the arithmetic: “time into frequency” yields cycles, and “cycles × bits per cycle” yields bit rate. The example illustrates how a parallel‑to‑serial conversion can slash bandwidth by a factor of four, even when clock speeds remain identical.

For hardware designers, this stark contrast underscores the need to consider serialization overhead when sizing interfaces, selecting clock rates, or planning system‑level bandwidth. Choosing higher‑frequency clocks, wider parallel buses, or more efficient serializers becomes essential for meeting performance targets.