Decoder Based RAM Design in Verilog | SystemVerilog Testbench Series Day 2

Why It Matters

A correctly decoded RAM design simplifies verification and scales to larger memories, reducing bugs in hardware projects.

Key Takeaways

• Decoder-based RAM splits 128 bytes into four 32‑byte blocks.
• 7‑bit address: top 2 bits select block, lower 5 select word.
• Chip‑select (CS) signals generated via 2‑to‑4 decoder logic.
• Write/read logic uses CS and word address to access correct block.
• Testbench will verify block selection, write, and read operations.

Summary

The video walks through a Verilog implementation of a decoder‑based RAM module, the second installment of a SystemVerilog testbench series. It outlines the architecture of a 128‑byte memory organized as four 32‑byte blocks, each accessed via a 7‑bit address where the two most‑significant bits select the block and the remaining five bits select the word within that block. Key design details include a 2‑to‑4 decoder that generates one‑hot chip‑select (CS) signals, internal word‑address extraction, and separate always blocks for asynchronous reset, write, and read operations. The presenter demonstrates how to instantiate four memory arrays, initialize them on reset, and conditionally route write data (W_data) or read data (R_data) based on CS and the decoded word address. Examples illustrate that an address of 00xxxxxx selects block 0, while 01xxxxxx selects block 1, and so on. The code snippets show CS assignment logic, block‑specific write cases (e.g., CS=0010 writes to block 1), and read cases that output data and a valid flag only when read enable is asserted. The walkthrough emphasizes modular coding practices and sets the stage for a comprehensive testbench that will exercise block selection, write, and read scenarios, highlighting the importance of clear address decoding in scalable memory designs.

Original Description

In Day 2 of the SystemVerilog Testbench series for Decoder-Based RAM Verification, we focus on designing the RAM architecture using Verilog.

Before writing a testbench, it is important to clearly define the Design Under Test (DUT). In this session, we implement a Decoder-Based RAM design in Verilog, which will later be verified using a SystemVerilog testbench.

In this video, you will learn:

Architecture of a Decoder-Based RAM

How an address decoder selects memory locations

Writing the Verilog RTL code for decoder-based RAM

Understanding the read and write operations in RAM

Preparing the design for SystemVerilog verification

This project-based series helps you understand how RTL design and verification work together in real VLSI projects.

Upcoming videos in this series will focus on:

Writing the SystemVerilog Testbench

Generating stimulus

Implementing checking and verification logic

If you want to learn VLSI Design and Verification with practical projects, make sure to follow the complete playlist.

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