Software to Silicon with RISC-V for Physical AI

Why It Matters

For chipmakers and cloud/AI customers, RISC‑V’s promise of a common, scalable ISA means lower cost, faster time‑to‑market and the ability to tune silicon for emerging AI workloads—crucial as demand surges and incumbents’ architectures prove inefficient. Strategic investments and acquisitions now determine which firms can meet unpredictable, high‑performance AI needs.

Summary

Speakers argued that RISC‑V is enabling a shift from one‑size‑fits‑all, software‑defined system designs to workload‑optimized, customizable silicon, letting companies tailor cores and accelerators to peak needs rather than buying generic overprovisioned architectures. They placed that technical pivot in a business context: markets move faster than product roadmaps, so MIP, GlobalFoundries and ARC accelerated M&A and investment to deliver scalable RISC‑V solutions across MCUs, NPUs and GPUs. Panelists traced the inefficiencies of past heterogeneous SOC choices—especially memory bloat—and said a single, extensible ISA simplifies programming and reduces wasted resources. The conversation tied this trend to the rapid emergence of agentic and generative AI workloads that demand faster, more efficient hardware customization.

Original Description

Nitin Dahad of EE Times moderates a panel with Sameer Wasson, CEO of MIPS, by GF, and Andrea Gallo, CEO of RISC-V International for a conversation on how the industry must rethink chip design for Agentic AI. Topics covered:

• GlobalFoundries’ acquisition of MIPS and the recent acquisition of the Synopsys ARC Processor IP solutions business and what it means for customers

• Why RISC-V is becoming the default ISA for new silicon designs

• The shift to software-first, workload-optimized architectures

• How MIPS Atlas Explorer virtual platforms shortens time to revenue

www.mips.com

https://risv.org

https://mips.com/products/software/mips-atlas-explorer/