SRAM Verilog Code Implementation | 6T SRAM Design in Verilog | VLSI Project Series

Why It Matters

A clear, simulation‑ready SRAM controller accelerates prototyping and education in digital design, reducing time spent on low‑level memory interfacing.

Key Takeaways

• SRAM controller written in Verilog with 8‑bit data, 8‑bit address.
• FSM includes idle, read, write, and done states.
• Chip‑select and write‑enable signals determine read vs write transition.
• Ready signal asserts only after transaction reaches done state.
• Testbench drives controller to verify read/write functionality effectively.

Summary

The video walks through a Verilog implementation of a simple 6T SRAM controller, detailing module ports, internal memory sizing, and the accompanying testbench used for simulation. It targets an educational VLSI project series, showing how to model SRAM behavior without physical hardware.

Key design elements include an 8‑bit address bus, 8‑bit data bus, and a 256‑location internal memory array. The controller operates as a finite‑state machine with four states—idle, read, write, and done—driven by chip‑select and write‑enable signals. Output‑enable (OE) and a ready flag are managed to indicate when data is valid and when a transaction completes.

The presenter highlights that during a read, OE is asserted high and data is routed from the memory array to the output, while a write keeps OE low and stores incoming data at the specified address. The ready signal is de‑asserted throughout the operation and only goes high in the done state, signaling transaction completion. A Vivado testbench exercises these paths, confirming correct read/write behavior.

For designers, this example provides a reusable template for SRAM interfacing, illustrating best practices for synchronous state handling, reset logic, and testbench verification. It also serves as a stepping stone toward more complex memory controllers in ASIC or FPGA projects.

Original Description

In this session of the VLSI Project Development Series, we move from theory to implementation by developing the Verilog code for an SRAM (Static Random Access Memory).

After understanding the 6T SRAM cell architecture in the previous session, we now focus on how to model SRAM behavior using Verilog. This includes implementing read and write operations, handling addressing, and understanding how memory arrays are described in RTL.

This session is crucial for bridging the gap between SRAM architecture and hardware implementation, helping you gain practical experience in memory design using Verilog.

🔍 What you will learn:

• Verilog modeling of SRAM

• Memory array declaration in Verilog

• Read and write operation logic

• Address decoding basics

• Simulation approach for SRAM design

💡 This is a key step in learning how real-world memory blocks are designed and implemented in digital systems.

📌 Next Step:

We will move towards testbench development and simulation to verify the SRAM design.

This series is perfect for anyone aiming to become a VLSI/RTL Design Engineer and learn through hands-on projects.

Hashtags:

#Verilog #SRAM #MemoryDesign #VLSI #RTLDesign #FPGA #DigitalDesign #ASICDesign #HardwareDesign #Semiconductor #ChipDesign #VerilogProjects #EngineeringStudents #VLSILearning #EmbeddedSystems #HardwareEngineering #DigitalElectronics #VLSIProjects #TechEducation #LearnVerilog