SystemVerilog Testbench Day 6 | Write Monitor Development | Decoder RAM Verification

Why It Matters

A dedicated write monitor captures stimulus accurately, enabling reliable scoreboard comparison and early detection of design bugs in RAM controllers.

Key Takeaways

• Write monitor samples write driver signals via virtual interface.
• Transactions are packaged into objects and forwarded to scoreboard and reference model.
• Mailbox handles enable communication between monitor, scoreboard, and reference model.
• New() method injects interface and mailbox instances from environment.
• Future steps include functional coverage integration and read monitor implementation.

Summary

The video walks through creating a write monitor component for a SystemVerilog testbench that verifies a decoder‑based RAM. After reviewing earlier sessions on functional coverage, transaction generation, and driver development, the presenter introduces the monitor’s role: sampling the write driver’s signals from a virtual interface and forwarding them for analysis. Key technical details include declaring a virtual RAM interface handle, two mailbox handles (scoreboard and reference model), and an internal transaction counter. The monitor’s New() method receives the interface and mailbox instances from the environment, ensuring proper connectivity without hard‑coding resources. In the run task, a forever loop waits on the clocking block, checks the write‑enable signal, captures address, data, and operation fields into a transaction object, prints the values, and pushes the transaction into both mailboxes. The presenter demonstrates concrete code snippets: virtual interface declaration, mailbox initialization, the conditional sampling of write_enable, and the population of txn.address, txn.wdata, and txn.op fields. He also notes the absence of a copy method in the transaction class, confirming that direct mailbox puts suffice for now. By integrating this monitor, verification engineers can compare driven transactions against a reference model and scoreboard, laying the groundwork for functional coverage insertion and subsequent read‑monitor development. This modular approach streamlines stimulus capture and error detection in memory controller verification.

Original Description

In Day 6 of the SystemVerilog Testbench series for Decoder-Based RAM, we focused on developing the Write Monitor, an important component in the verification environment.

The Monitor observes the DUT signals through the interface and captures the activity without driving anything. In this session, we implemented the Write Monitor to track write operations and convert signal-level activity back into transactions.

In this session we covered:

• Development of the Write Monitor

• Understanding how the Monitor passively observes DUT signals

• Converting signal-level activity into transaction-level data

• Role of the Monitor in the verification flow

The monitor will play a key role in the next stages, where we will:

• Write proper test cases

• Introduce a coverage model to measure verification completeness

This session helps in understanding how data is captured from the DUT and prepared for further analysis like checking and coverage.

Hashtags:

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