Tech Podcast: Automated Multiphysics for 3D IC Success | EE Times Current
Why It Matters
Automated multiphysics verification shortens design cycles and mitigates costly failures in 3‑D ICs, directly impacting product launch speed and profitability for chipmakers.
Key Takeaways
- •3D IC stacking introduces new materials and heterogeneous processes challenges.
- •Thermal, mechanical, and power interactions must be analyzed early (shift‑left).
- •Integrated Calibre‑FlowTherm workflow automates detailed thermal modeling for designers.
- •Cross‑team collaboration and common language are essential for multi‑physics verification.
- •Chiplet‑level verification must consider stack‑level stress and timing impacts.
Summary
The EE Times Current podcast spotlights Siemens EDA’s push to automate multiphysics verification for true 3‑D ICs. Principal product manager Cheva Kalivar and senior technical director John Ferguson explain how the industry is moving beyond 2‑D and 2.5‑D designs toward heterogeneous stacks that combine diverse materials, processes, and chiplets.
They stress that the added dimension multiplies data volume and introduces thermal, mechanical and power‑density challenges that traditional EDA tools cannot handle. A “shift‑left” approach—embedding thermal and stress analysis at the front of the design flow—is essential to keep cycle times realistic. The conversation highlights the need for common languages across foundries, OSATs, and package designers to protect IP while enabling seamless collaboration.
A concrete example is Siemens EDA’s integration of Calibre with the FlowTherm solver. Calibre extracts detailed GDS‑II geometry—including wires, oxides and transistors—and feeds it into FlowTherm to generate accurate thermal models, which are then visualized back in the familiar Calibre environment. This automation lets a designer without deep thermal expertise evaluate heat‑induced stress and timing shifts, and make informed placement decisions early in the workflow.
The broader implication is a growing tool ecosystem and new standards to support full‑stack verification. Companies that adopt these automated, cross‑functional flows can reduce costly late‑stage re‑spins, accelerate time‑to‑market for AI‑centric chips, and maintain competitive advantage in an increasingly complex semiconductor landscape.
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